Method for increasing speed of writing data into flash memory unit and associated device

1. A method for writing data into a flash memory unit, the method comprising:

when writing data into the flash memory unit for the n-th time, determining a data polarity of an n-th data bit to be written into the flash memory unit;

selectively injecting an n-th electrical charge amount into a floating gate of the flash memory unit according to the data polarity of the n-th data bit only;

when writing data into the flash memory unit for the (n+1)-th time, determining the data polarity of an (n+1)-th data bit to be written into the flash memory unit; and

selectively injecting an (n+1)-th electrical charge amount into the floating gate of the flash memory unit according to the data polarity of the (n+1)-th data bit only;

wherein the (n+1)-th electrical charge amount is not equal to the n-th electrical charge amount, and n is a positive integer not less than 1.

2. The method of claim 1 , wherein the (n+1)-th electrical charge amount is at least double the n-th electrical charge amount.

3. The method of claim 1 , wherein when writing data into flash memory unit for the n-th time, if the data polarity of the n-th data bit is a first polarity, not injecting the n-th electrical charge amount to the floating gate, and if the data polarity of the n-th data bit is a second polarity, injecting the n-th electrical charge amount to the floating gate; and when writing data into the flash memory unit for the (n+1)-th time, if the data polarity of the (n+1)-th data bit is the first polarity, not injecting the (n+1)-th electrical charge amount to the floating gate, and if the data polarity of the (n+1)-th data bit is the second polarity, injecting the (n+1)-th electrical charge amount to the floating gate, wherein the first polarity is different from the second polarity.

4. The method of claim 3 , wherein the first polarity is bit 1 , and the second polarity is bit 0 ; or the first polarity is bit 0 , and the second polarity is bit 1 .

5. The method of claim 3 , wherein if the data polarity of the n-th data bit is the first polarity, the method further comprises:

determining an n-th threshold voltage;

wherein when the n-th threshold voltage is coupled to a control gate of the flash memory unit, the n-th threshold voltage turns on the flash memory unit which is not injected with the n-th electrical charge amount.

6. The method of claim 5 , wherein if the data polarity of the (n+1)-th data bit is the first polarity, the method further comprises:

determining an (n+1)-th threshold voltage;

wherein when the (n+1)-th threshold voltage is coupled to the control gate of the flash memory unit, the (n+1)-th threshold voltage turns on the flash memory unit which is not injected with the (n+1)-th electrical charge amount, and the (n+1)-th threshold voltage is at least double the n-th threshold voltage.

7. The method of claim 5 , wherein if the data polarity of the (n+1)-th data bit is the second polarity, the method further comprises:

determining an (n+1)-th threshold voltage;

wherein when the (n+1)-th threshold voltage is coupled to the control gate of the flash memory unit, the (n+1)-th threshold voltage does not turn on the flash memory unit which is injected with the (n+1)-th electrical charge amount, and the (n+1)-th threshold voltage is at least double the n-th threshold voltage.

8. The method of claim 3 , wherein if the data polarity of the n-th data bit is the second polarity, the method further comprises:

determining an n-th threshold voltage;

wherein when the n-th threshold voltage is coupled to a control gate of the flash memory unit, the n-th threshold voltage does not turn on the flash memory unit which is injected with the n-th electrical charge amount.

9. The method of claim 8 , wherein if the data polarity of the (n+1)-th data bit is the first polarity, the method further comprises:

determining an (n+1)-th threshold voltage;

wherein the (n+1)-th threshold voltage is coupled to the control gate of the flash memory unit, the (n+1)-th threshold voltage turns on the flash memory unit which is not injected with the (n+1)-th electrical charge amount, and the (n+1)-th threshold voltage is at least double the n-th threshold voltage.

10. The method of claim 8 , wherein if the data polarity of the (n+1)-th data bit is the second polarity, the method further comprises:

determining an (n+1)-th threshold voltage;

wherein the (n+1)-th threshold voltage is coupled to the control gate of the flash memory unit, the (n+1)-th threshold voltage does not turn on the flash memory unit which is injected with the (n+1)-th electrical charge amount, and the (n+1)-th threshold voltage is at least double the n-th threshold voltage.

11. A control device, arranged to write data into a flash memory unit, the control device comprising:

a determining circuit, arranged to determine a data polarity of an n-th data bit of the flash memory unit when writing data into the flash memory unit for the n-th time; and

a writing circuit, arranged to inject an n-th electrical charge amount to a floating gate of the flash memory unit according to the data polarity of the n-th data bit only;

wherein the determining circuit is further arranged to determine the data polarity of an (n+1)-th data bit of the flash memory unit when writing data into the flash memory unit for the (n+1)-th time, the writing circuit is further arranged to selectively inject an (n+1)-th electrical charge amount to the floating gate of the flash memory unit according to the data polarity of the (n+1)-th data bit only, the (n+1)-th electrical charge amount is not equal to the n-th electrical charge amount, and n is a positive integer not smaller than 1.

12. The control device of claim 11 , wherein the (n+1)-th electrical charge amount is at least double the n-th electrical charge amount.

13. The control device of claim 11 , wherein when writing data into the flash memory unit for the n-th time, if the determining circuit determines that the data polarity of the n-th data bit is a first polarity, the writing circuit does not inject the n-th electrical charge amount into the floating gate, if the determining circuit determines that the data polarity of the n-th data bit is a second polarity, the writing circuit injects the n-th electrical charge amount into the floating gate; and when writing data into the flash memory unit for the (n+1)-th time, if the determining circuit determines that the flash memory unit of the (n+1)-th data bit is the first polarity, the writing circuit does not inject the (n+1)-th electrical charge amount into the floating gate, and if the determining circuit determines that the data polarity of the (n+1)-th data bit is the second polarity, the writing circuit injects the (n+1)-th electrical charge amount into the floating gate, wherein the first polarity is not equal to the second polarity.

14. The control device of claim 13 , wherein the first polarity is bit 1 , and the second polarity is bit 0 ; or the first polarity is bit 0 , and the second polarity is bit 1 .

15. The control device of claim 13 , wherein if the data polarity of the n-th data bit is the first polarity, the control circuit further comprises:

a setting circuit, arranged to determine an n-th threshold voltage;

wherein when the n-th threshold voltage is coupled to a control gate of the flash memory unit, the n-th threshold voltage turns on the flash memory unit which is not injected with the n-th electrical charge amount.

16. The control device of claim 15 , wherein if the data polarity of the (n+1)-th data bit is the first polarity, the control circuit further comprises:

a setting circuit, arranged to determine an (n+1)-th threshold voltage;

wherein when the (n+1)-th threshold voltage is coupled to the control gate of the flash memory unit, the (n+1)-th threshold voltage turns on the flash memory unit which is not injected with the (n+1)-th electrical charge amount, and the (n+1)-th threshold voltage is at least double the n-th threshold voltage.

17. The control device of claim 15 , wherein if the data polarity of the (n+1)-th data bit is the second polarity, the control circuit further comprises:

a setting circuit, arranged to determine an (n+1)-th threshold voltage;

wherein when the (n+1)-th threshold voltage is coupled to the control gate of the flash memory unit, the (n+1)-th threshold voltage does not turn on the flash memory unit which is injected with the (n+1)-th electrical charge amount, and the (n+1)-th threshold voltage is at least double the n-th threshold voltage.

18. The control device of claim 13 , wherein if the data polarity of the n-th data bit is the second polarity, the control circuit further comprises:

a setting circuit, determining an n-th threshold voltage;

wherein when the n-th threshold voltage is coupled to a control gate of the flash memory unit, the n-th threshold voltage does not turn on the flash memory unit which is injected with the n-th electrical charge amount.

19. The control device of claim 18 , wherein if the data polarity of the (n+1)-th data bit is the first polarity, the control circuit further comprises:

a setting circuit, determining an (n+1)-th threshold voltage;

wherein when the (n+1)-th threshold voltage is coupled to the control gate of the flash memory unit, the (n+1)-th threshold voltage turns on the flash memory unit which is not injected with the (n+1)-th electrical charge amount, and the (n+1)-th threshold voltage is at least double the n-th threshold voltage.

20. The control device of claim 18 , wherein if the data polarity of the (n+1)-th data bit is the second polarity, the control circuit further comprises:

a setting circuit, determining an (n+1)-th threshold voltage;

wherein when the (n+1)-th threshold voltage is coupled to the control gate of the flash memory unit, the (n+1)-th threshold voltage does not turn on the flash memory unit which is injected with the (n+1)-th electrical charge amount, and the (n+1)-th threshold voltage is at least double the n-th threshold voltage.