Memory operating method for increasing cell capacity based on resistance characteristic of memory and associated memory device

1. A memory operating method, comprising:

applying a first read voltage to a memory cell having a plurality of resistance levels, wherein the memory cell is a multi-level-cell of a phase change memory; and

applying a second read voltage to the memory cell when failing to read data of the memory cell under the first read voltage;

wherein the second read voltage is set to larger than the first read voltage when a resistance of the memory cell under the first read voltage is larger than an upper resistance limit of a resistance sensing window; and

the second read voltage is set to smaller than the first read voltage when the resistance value of the memory cell under the first read voltage is smaller than a lower resistance limit of the resistance sensing window;

wherein the resistance sensing window has the upper resistance limit and the lower resistance limit between which data corresponding to a resistance level exhibited by the memory cell is configured to be read.

2. The memory operating method according to claim 1 , wherein the first read voltage is 0.3V to 0.5V;

when the resistance of the memory cell under the first read voltage is larger than the upper resistance limit of the resistance sensing window, the second read voltage is 0.8V to 0.9V, or larger than 0.9V; and

when the resistance value of the memory cell under the first read voltage is smaller than the lower resistance limit of the resistance sensing window, the second read voltage is 0.1V to 0.2V.

3. The memory operating method according to claim 1 , wherein the resistance sensing window is ranged from 100 Kohm to 1 Mohm.

4. The memory operating method according to claim 1 , further comprising:

applying a third read voltage to the memory cell when failing to read data of the memory cell under the second read voltage.

5. The memory operating method according to claim 4 , wherein the third read voltage is larger than both the second read voltage and the first read voltage.

6. The memory operating method according to claim 5 , wherein the first read voltage is 0.1V to 0.2V.

7. The memory operating method according to claim 5 , wherein the second read voltage is 0.3V to 0.5V when the resistance of the memory cell under the first read voltage is larger than the upper resistance limit of the resistance sensing window.

8. The memory operating method according to claim 5 , wherein the third read voltage is 0.8V to 0.9V, or larger than 0.9V.

9. The memory operating method according to claim 1 , wherein the first read voltage is to sense a first group of the data levels, and the second read voltage is to sense a second group of the data levels.

10. The memory operating method according to claim 1 , further comprising:

under the first read voltage, determining whether the resistance of the memory cell corresponding to write data is within the resistance sensing window;

if yes, programming and verifying the memory cell with the first read voltage; and

if not, programming and verifying the memory cell with the second read voltage.

11. The memory operating method according to claim 10 , wherein the second read voltage is 0.8V to 0.9V, or larger than 0.9V, when the resistance of the memory cell corresponding to the write data exceeds the resistance sensing window under the first read voltage.

12. The memory operating method according to claim 10 , wherein the second read voltage is 0.1V to 0.2V when the resistance of the write data is lower than the resistance sensing window.

13. A memory device, comprising:

a memory array including at least one memory cell having a plurality of resistance levels to store data, wherein the at least one memory cell is a multi-level-cell of a phase change memory; and

a controller, coupled to the memory array, applying a first read voltage to the at least one memory cell and applying a second read voltage to the at least one memory cell when failing to read the data under the first read voltage;

wherein the second read voltage is set to larger than the first read voltage when a resistance of the memory cell under the first read voltage is larger than an upper resistance limit of a resistance sensing window; and

the second read voltage is set to smaller than the first read voltage when the resistance value of the memory cell under the first read voltage is smaller than a lower resistance limit of the resistance sensing window;

wherein the resistance sensing window has the upper resistance limit and the lower resistance limit between which data corresponding to a resistance level exhibited by the memory cell is configured to be read.

14. The memory device according to claim 13 , wherein the first read voltage is to sense one group of the data levels, and the second read voltage is to sense another one group of the data levels.

15. The memory device according to claim 14 , wherein the first read voltage is 0.3V to 0.5V.

16. The memory device according to claim 15 , wherein the second read voltage is 0.1V to 0.2V when the resistance value of the memory cell under the first read voltage is smaller than the lower resistance limit of the resistance sensing window.

17. The memory device according to claim 15 , wherein the second read voltage is 0.8V to 0.9V, or larger than 0.9V when the resistance of the memory cell under the first read voltage is larger than the upper resistance limit of the resistance sensing window.

18. The memory device according to claim 13 , wherein the controller determines whether the resistance of the memory cell corresponding to write data is within the resistance sensing window under the first read voltage;

if yes, the controller programs and verifies the at least one memory cell with the first read voltage; and

if not, the controller programs and verifies the at least one memory cell with the second read voltage.