IP Library Granted Patent US 9,628,655
Granted Patent B2
US 9,628,655 · App. 15/141,341 · Granted Apr 18, 2017

Image forming apparatus and image forming method that are normally resettable in mode where operating voltage is not supplied to main CPU

Inventor: Katsuo Mikashima (Osaka, JP)
Assignee: KYOCERA Document Solutions Inc.
H04N1/00899
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Quick Facts
Patent No.
US 9,628,655
App. No.
15/141,341
Granted
Apr 18, 2017
Kind
B2
Abstract

An image forming apparatus includes a main CPU, a sub CPU, a mode control circuit, a voltage monitoring circuit, a reset circuit, and a prevention circuit. The voltage monitoring circuit outputs a first abnormality detection signal if the operating voltage supplied to the main CPU is determined as abnormal. The voltage monitoring circuit outputs a second abnormality detection signal if the operating voltage supplied to the sub CPU is determined as abnormal. The reset circuit resets the main CPU and the sub CPU if at least one of the first abnormality detection signal and the second abnormality detection signal is transmitted. The prevention circuit prevents the transmission of the first abnormality detection signal to the reset circuit in the second mode.

Claims (33)

1. An image forming apparatus, comprising:

a main CPU that controls the image forming apparatus;

a sub CPU that controls a predetermined function of the image forming apparatus, the sub CPU having a power consumption smaller than a power consumption of the main CPU;

a mode control circuit that controls switching between a first mode and a second mode, the first mode supplying the main CPU and the sub CPU with an operating voltage, the second mode supplying the sub CPU with the operating voltage without supplying the main CPU with the operating voltage;

a voltage monitoring circuit that outputs a first abnormality detection signal if the operating voltage supplied to the main CPU is determined as abnormal, the voltage monitoring circuit outputting a second abnormality detection signal if the operating voltage supplied to the sub CPU is determined as abnormal;

a reset circuit that resets the main CPU and the sub CPU if at least one of the first abnormality detection signal and the second abnormality detection signal is transmitted; and

a prevention circuit that prevents the transmission of the first abnormality detection signal to the reset circuit in the second mode,

wherein the prevention circuit includes a first mask circuit that causes the first abnormality detection signal to pass through the first mask circuit and to be transmitted to the reset circuit in the first mode, the first mask circuit cutting off the first abnormality detection signal and transmitting a signal indicating that the operating voltage supplied to the main CPU is normal, to the reset circuit in the second mode.

2. The image forming apparatus according to claim 1 ,

wherein the prevention circuit controls the voltage monitoring circuit, in the second mode, to cause the voltage monitoring circuit to stop monitoring whether or not the operating voltage supplied to the main CPU is abnormal, and to transmit a signal indicating the operating voltage supplied to the main CPU is normal to the reset circuit.

3. An image forming apparatus, comprising:

a main CPU that controls the image forming apparatus;

a sub CPU that controls a predetermined function of the image forming apparatus, the sub CPU having a power consumption smaller than a power consumption of the main CPU;

a mode control circuit that controls switching between a first mode and a second mode, the first mode supplying the main CPU and the sub CPU with an operating voltage, the second mode supplying the sub CPU with the operating voltage without supplying the main CPU with the operating voltage;

a voltage monitoring circuit that outputs a first abnormality detection signal if the operating voltage supplied to the main CPU is determined as abnormal, the voltage monitoring circuit outputting a second abnormality detection signal if the operating voltage supplied to the sub CPU is determined as abnormal;

a reset circuit that resets the main CPU and the sub CPU if at least one of the first abnormality detection signal and the second abnormality detection signal is transmitted;

a prevention circuit that prevents the transmission of the first abnormality detection signal to the reset circuit in the second mode,

wherein when the main CPU and the sub CPU are reset in the first mode, the reset circuit releases the resets of the main CPU and the sub CPU after a lapse of a first predetermined period of time since the resets are started,

when the sub CPU is reset while the main CPU is not supplied with the operating voltage and the main CPU is reset in the second mode, the reset circuit releases the resets of the main CPU and the sub CPU after a lapse of a second predetermined period of time since the resets are started;

wherein the image forming apparatus further includes a power supply control circuit,

the power supply control circuit stops supplying the operating voltage to the main CPU and the sub CPU after the resets of the main CPU and the sub CPU are started, and resumes supplying the operating voltage to the main CPU and the sub CPU before the resets of the main CPU and the sub CPU are released in the first mode, and

the power supply control circuit stops supplying the operating voltage to the sub CPU after the reset of the sub CPU is started, and resumes supplying the operating voltage to the main CPU and the sub CPU before the resets of the main CPU and the sub CPU are released in the second mode.

4. An image forming apparatus, comprising:

a main CPU that controls the image forming apparatus;

a sub CPU that controls a predetermined function of the image forming apparatus, the sub CPU having a power consumption smaller than a power consumption of the main CPU;

a mode control circuit that controls switching between a first mode and a second mode, the first mode supplying the main CPU and the sub CPU with an operating voltage, the second mode supplying the sub CPU with the operating voltage without supplying the main CPU with the operating voltage;

a voltage monitoring circuit that outputs a first abnormality detection signal if the operating voltage supplied to the main CPU is determined as abnormal, the voltage monitoring circuit outputting a second abnormality detection signal if the operating voltage supplied to the sub CPU is determined as abnormal;

a reset circuit that resets the main CPU and the sub CPU if at least one of the first abnormality detection signal and the second abnormality detection signal is transmitted;

a prevention circuit that prevents the transmission of the first abnormality detection signal to the reset circuit in the second mode,

wherein the mode control circuit controls to switch from the first mode to the second mode when a switching signal indicating an instruction for switching from the first mode to the second mode is transmitted from the main CPU,

wherein the image forming apparatus further includes a second mask circuit,

the second mask circuit causes the switching signal to pass through the second mask circuit and causes the switching signal to be transmitted to the mode control circuit when the voltage monitoring circuit determines the operating voltage supplied to the main CPU is not abnormal in the first mode, and

the second mask circuit cuts off the switching signal not to be transmitted to the mode control circuit when the voltage monitoring circuit determines the operating voltage supplied to the main CPU is abnormal in the first mode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2016
From: MIKASHIMA, KATSUO
To: KYOCERA DOCUMENT SOLUTIONS INC.
Reel/Frame 038419/0696 →
Priority Claims (1)
JP 2015-096296 · May 11, 2015 · national
Continuity (1)
Related Publication 20160337528A1 · Nov 17, 2016