Device and method for communicating between cores

1. A device for communicating between cores, comprising:

a postbox component, performed by the hardware processor, configured to store a message sent from a message sending core to a message receiving core and notify the message receiving core to read the message; and

a bus adapter, connected between the postbox component and the message receiving core and the message sending core which communicate with each other and configured to provide read/write interfaces of the postbox component and the message receiving core and the message sending core;

wherein the postbox component comprises: a bus interface element, configured to achieve a mutual exclusion of a read/write message by multiplexing a bus error feedback register; wherein the bus interface element comprises: a first mutual exclusion element, configured to achieve a function of a mutual exclusion lock by multiplexing the bus error feedback register, so as to achieve a mutual exclusion of a plurality of message sending cores writing messages to the postbox component; and/or a second mutual exclusion element, configured to achieve a function of a mutual exclusion lock by multiplexing the bus error feedback register, so as to achieve a mutual exclusion of a message sending core writing a message to the postbox component and a message receiving core reading a message from the postbox component;

a triggering subelement, configured to trigger a state of the bus error feedback register to change after the message sending core writes a message to the postbox component, or the message receiving core reads a message from the postbox component,

the postbox component sends a first response message to the message sending core after the message sending core writes a message to the postbox component, wherein the message sending core determines that the message sending core successfully writes the message to the postbox component according to the first response message; and/or

the postbox component sends a second response message to the message receiving core after the message receiving core reads a message from the postbox component, wherein the message receiving core determines that the message receiving core successfully reads the message according to the second response message.

2. The device according to claim 1 , further comprising:

an arbiter component, configured to, when a plurality of cores simultaneously initiate read/write access requests for requesting a read/write message to the postbox component, arbitrate a plurality of read/write access requests according to a predetermined rule and output the plurality of read/write access requests serially and sequentially.

3. The device according to claim 1 , wherein the postbox component comprises:

a storage element, configured to store the message according to a message access address.

4. The device according to claim 1 , wherein the postbox component comprises:

a notifying element, configured to notify the message receiving core to receive a message by an interrupt request.

5. A method for communicating between cores, comprising:

receiving, by a postbox component, a message sent from a message sending core through a bus adapter component; and

sending, by the postbox component, an interrupt request to a message receiving core, wherein the message receiving core reads the message according to the interrupt request;

wherein when a plurality of cores simultaneously initiate read/write access requests for requesting a read/write message to the postbox component, achieving a mutual exclusion of the read/write message by multiplexing a bus error feedback register; wherein achieving the mutual exclusion of the read/write message by multiplexing a bus error feedback register comprises: achieving a function of a mutual exclusion lock by multiplexing the bus error feedback register, so as to achieve a mutual exclusion of a plurality of message sending cores writing messages to the postbox component; and/or achieving a function of a mutual exclusion lock by multiplexing the bus error feedback register, so as to achieve a mutual exclusion of a message sending core writing a message to the postbox component and a message receiving core reading a message from the postbox component;

triggering a state of the bus error feedback register to change after the message sending core writes a message to the postbox component, or the message receiving core reads a message from the postbox component;

the postbox component sends a first response message to the message sending core after the message sending core writes a message to the postbox component, wherein the message sending core determines that the message sending core successfully writes the message to the postbox component according to the first response message; and/or

the postbox component sends a second response message to the message receiving core after the message receiving core reads a message from the postbox component, wherein the message receiving core determines that the message receiving core successfully reads the message according to the second response message.

6. The method according to claim 5 , further comprising: when a plurality of cores simultaneously initiate read/write access requests for requesting a read/write message to the postbox component, arbitrating a plurality of read/write access requests according to a predetermined rule and outputting the plurality of read/write access requests serially and sequentially.

7. The method according to claim 5 , further comprising clearing, by the postbox component, the interrupt request after the message receiving core receives the message.

8. A device for communicating between cores, comprising:

a receiving element, located in a postbox component, configured to receive a message sent from a message sending core through a bus adapter component; and

a sending element, located in the postbox component, configured to send an interrupt request to a message receiving core, wherein the message receiving core reads the message according to the interrupt request;

a bus interface element, located in the postbox component, configured to achieve a mutual exclusion of a read/write message by multiplexing a bus error feedback register; wherein the bus interface element comprises: a first mutual exclusion element, configured to achieve a function of a mutual exclusion lock by multiplexing the bus error feedback register, so as to achieve a mutual exclusion of a plurality of message sending cores writing messages to the postbox component; and/or a second mutual exclusion element, configured to achieve a function of a mutual exclusion lock by multiplexing the bus error feedback register, so as to achieve a mutual exclusion of a message sending core writing a message to the postbox component and a message receiving core reading a message from the postbox component;

a triggering subelement, configured to trigger a state of the bus error feedback register to change after the message sending core writes a message to the postbox component, or the message receiving core reads a message from the postbox component,

the postbox component sends a first response message to the message sending core after the message sending core writes a message to the postbox component, wherein the message sending core determines that the message sending core successfully writes the message to the postbox component according to the first response message; and/or

the postbox component sends a second response message to the message receiving core after the message receiving core reads a message from the postbox component, wherein the message receiving core determines that the message receiving core successfully reads the message according to the second response message.