Two-way parity error detection for advanced encryption standard engines
A method of improving the operation of a processor executing a cryptographic process, by automatically detecting faults during both encryption and decryption operations by the cryptographic process, comprises segmenting the data to be encrypted and encrypting the data segments using a complex non-linear algorithm that can lead to faults; computing an output parity bit from a selected step of the algorithm for a selected data segment, based on the input value of that segment; comparing the actual output parity bit of the selected segment with the computed output parity bit for that segment; and determining whether a fault exists, based on whether the actual output parity bit matches the computed output parity bit for the selected segment.
1. An encryption engine using two-way parity fault detection, the encryption engine including:
a) an S-box/invert S-box (SBISB) processor implemented by at least one hardware device, having an input and an output;
b) a first one-bit parity computer having an input and an output, the input coupled to the input of the SBISB processor, the first one-bit parity computer configured to compute the one-bit parity of the output of the SBISB processor based on the input to the SBISB processor;
c) a first parity comparator implemented by at least one hardware device, having a first and second input and an output, the first input coupled to the output of the first one-bit parity computer and the second input coupled to the output of the SBISB processor, the first parity comparator configured to compare the output of the first one-bit parity computer to the actual parity of the output of the SBISB processor;
d) a second one-bit parity computer having an input and an output, the input coupled to the output of the SBISB processor, the second one-bit parity computer configured to compute the one-bit parity of the input to the SBISB processor based on the output of the SBISB processor; and
e) a second parity comparator implemented by at least one hardware device, having a first and second input, the first input coupled to the output of the second one-bit parity computer and the second input coupled to the input of the SBISB processor, the second parity comparator configured to compare the output of the second one-bit parity computer to the actual parity of the input of the SBISB; the encryption engine, further including,
f) a shift rows/invert shift rows (SRISR) processor having an input coupled to the output of the SBISB processor and having an output;
g) an encrypt/decrypt processor having an input coupled to the output of the SRISR processor and having an output;
h) a mix column/invert mix column MCIMC processor having an input coupled to the output of the encrypt/decrypt processor and having an output;
i) a third one-bit parity computer having an input and an output, the input coupled to the input of the MCIMC processor, the third one-bit parity computer configured to compute the one-bit parity of the output of the MCIMC processor based on the input to the MCIMC processor;
j) a third parity comparator having a first and second input and an output, the first input coupled to the output of the third one-bit parity computer and the second input coupled to the output of the MCIMC processor, the third parity comparator configured to compare the output of the third one-bit parity computer to the actual parity of the output of the MCIMC processor;
k) a fourth one-bit parity computer having an input and an output, the input coupled to the output of the MCIMC processor, the fourth one-bit parity computer configured to compute the one-bit parity of the input to the MCIMC processor based on the output of the MCIMC processor; and
l) a fourth parity comparator having a first and second input, the first input coupled to the output of the fourth one-bit parity computer and the second input coupled to the input of the MCIMC processor, the fourth parity comparator configured to compare the output of the fourth one-bit parity computer to the actual parity of the input of the MCIMC processor.
2. The encryption engine of claim 1 , further including:
a) a fifth one-bit parity computer having an input and an output, the input coupled to the input of the MCIMC processor, the fifth one-bit parity computer configured to compute the one-bit parity of the input to the SBISB processor based on the input to the MCIMC processor; and
b) a fifth parity comparator implemented by at least one hardware device, having a first and second input, the first input coupled to the output of the fifth one-bit parity computer and the second input coupled to the input to the SBISB processor, the fifth parity comparator configured to compare the output of the fifth one-bit parity computer to the actual parity of the input of the SBISB processor.