Group III-nitride-based enhancement mode transistor having a heterojunction fin structure

1. A Group III-nitride-based enhancement mode transistor comprising a substrate, a buffer layer formed on the substrate, a body region formed on the buffer layer, a heterojunction fin structure comprising a plurality of fins, each fin being formed on the body region, and a Group III-nitride cap layer arranged on a top face of the heterojunction fin structure, wherein the heterojunction fin structure completely extends from a source of the transistor to a drain of the transistor, wherein the heterojunction fin comprises a plurality of mesas comprising a Group III-nitride barrier layer stacked on a Group III-nitride channel layer and forming a heterojunction with the Group III-nitride channel layer, and a Group III-nitride interlayer arranged between the Group III-nitride barrier layer and the Group III-nitride channel layer, wherein a continuous portion of the body region provides a base region that is disposed below the plurality of the fins and provides the Group III-nitride channel layer of each fin.

2. The Group III-nitride-based enhancement mode transistor of claim 1 , further comprising a gate electrode arranged on the Group III-nitride barrier layer.

3. The Group III-nitride-based enhancement mode transistor of claim 1 , wherein the heterojunction fin structure is deposited on a substrate.

4. The Group III-nitride-based enhancement mode transistor of claim 1 , further comprising a Group III-nitride back barrier layer.

5. The Group III-nitride-based enhancement mode transistor of claim 1 , further comprising a gate electrode arranged on the heterojunction fin structure, the gate electrode extending into regions between neighbouring fins of the heterojunction fin structure.

6. The Group III-nitride-based enhancement mode transistor of claim 1 , further comprising a gate electrode arranged on the Group III-nitride barrier layer, and wherein the fins extend from the source arranged adjacent a first side of the semiconductor body to the drain which is arranged adjacent an opposing side of the semiconductor body and have a strip-like form.

7. A semiconductor device comprising:

a Group III-nitride-based transistor having a fin structure,

a p-type Group III-nitride layer arranged on at least one of a side face and a top face of at least one fin of the fin structure;

a metal gate electrode arranged on the p-type Group III-nitride layer;

wherein the Group III-nitride-based transistor is an enhancement mode device, and

wherein a total contact area between the gate and the p-type Group III-nitride layer is less than a surface area of the upper surface of the p-type Group III-nitride layer.

8. The semiconductor device of claim 7 , wherein the fin structure comprises a first Group III-nitride semiconductor layer arranged on a second Group III-nitride semiconductor layer so as to form a heterojunction arranged within a fin of the fin structure.

9. The semiconductor device of claim 7 , wherein the p-type Group III-nitride layer is positioned underneath the gate electrode and has a total lateral area that is greater than that of the gate.