High capacity memory system using standard controller component
The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.
1. A memory module comprising:
a plurality of device sites;
a data buffer component coupled to the plurality of device sites;
at least eighteen dynamic random access memory (DRAM) devices disposed at respective device sites;
nine data buffer components coupled to the at least eighteen DRAM devices, each of the nine data buffer components being coupled to a respective pair of the at least eighteen DRAM devices, wherein the nine data buffer components includes the data buffer component; and
a command and address (CA) buffer component coupled to the at least eighteen DRAM devices, wherein the data buffer component is to couple to point-to-point data-links of a memory channel, wherein the data buffer component comprises:
three primary ports to couple to three multi-drop data-links in a first mode and to couple to three point-to-point data-links in a second mode; and
three secondary ports coupled to three of the at least eighteen DRAM devices.
2. The memory module of claim 1 , wherein the data buffer component is programmed to operate as a repeater.
3. The memory module of claim 1 , wherein the data buffer component is programmed to operate as a multiplexer.
4. The memory module of claim 1 , wherein the data buffer component is to couple to point-to-point data-links of a memory channel, wherein the point-to-point data-links do not connect to all other memory modules connected to a memory controller to which the memory module is connected.
5. The memory module of claim 1 , wherein the data buffer component is to couple to point-to-point data-links of a memory channel, wherein the point-to-point data-links are at least one of point-to-point (P-to-P) links or point-to-two-points (P-to-2P) links.
6. The memory module of claim 1 , further comprising a private bus coupled between at least two of the nine data buffer components.
7. The memory module of claim 1 , wherein at least one of the plurality of device sites comprises at least one of a single device, a two-package stack, at least a two-die stack, or a four-die stack with a micro-buffer component.
8. A memory module comprising:
a plurality of device sites;
a data buffer component coupled to the plurality of device sites, and wherein the data buffer component comprises:
two primary ports to couple to two data-links;
two secondary ports coupled to two of the plurality of device sites;
a first bi-directional path between a first primary port of the two primary ports and a first secondary port of the two secondary ports;
a second bi-directional path between a second primary port of the two primary ports and a second secondary port of the two secondary ports; and
a third bi-directional path between the first primary port and the second secondary port, wherein the data buffer component is to couple to point-to-point data-links of a memory channel, wherein the point-to-point data-links do not connect to all other memory modules connected to a memory controller to which the memory module is connected.
9. The memory module of claim 8 , wherein the data buffer component further comprises a fourth bi-directional path between the second primary port and the first secondary port.
10. The memory module of claim 8 , further comprising a plurality of dynamic random access memory (DRAM) devices disposed at respective device sites, wherein the data buffer component is to couple to point-to-point data-links of a memory channel, wherein the point-to-point data-links are at least one of point-to-point (P-to-P) links or point-to-two-points (P-to-2P) links.
11. The memory module of claim 8 , further comprising:
a plurality of dynamic random access memory (DRAM) devices disposed at respective of device sites; and
a plurality of data buffer components coupled to the plurality of DRAM devices.
12. The memory module of claim 8 , further comprising:
eighteen dynamic random access memory (DRAM) devices disposed at the respective device sites;
nine data buffer components coupled to the eighteen DRAM devices, each of the nine data buffer components being coupled to a pair of the eighteen DRAM devices, wherein the nine data buffer components includes the data buffer component; and
a command and address (CA) buffer component coupled to the eighteen DRAM devices.
13. A memory module comprising:
a plurality of device sites; and
a data buffer component coupled to the plurality of device sites, wherein the data buffer component further comprises:
a first multiplexer comprising two inputs coupled to two primary ports and an output coupled to a second secondary port of two secondary ports;
a second multiplexer comprising two inputs coupled to the two primary ports and an output coupled to a first secondary port of the two secondary ports;
a third multiplexer comprising two inputs coupled to the two secondary ports and an output coupled to a first primary port of the two primary ports; and
a fourth multiplexer comprising two inputs coupled to the two secondary ports and an output coupled to a second primary port of the two primary ports, wherein the data buffer component further comprises:
first synchronization logic coupled between the output of the first multiplexer and the second secondary port;
second synchronization logic coupled between the output of the second multiplexer and the first secondary port;
third synchronization logic coupled between the output of the third multiplexer and the first primary port; and
fourth synchronization logic coupled between the output of the fourth multiplexer and the second primary port.
14. The memory module of claim 13 , wherein the data buffer component further comprises:
a first bypass path from the first primary port to a third input of the fourth multiplexer; and
a second bypass path from the second primary port to a third input of the third multiplexer.
15. The memory module of claim 13 , wherein the data buffer component further comprises:
a fifth multiplexer comprising two inputs coupled to an output of the third synchronization logic and a first bypass path coupled the second primary port and an output coupled to the first primary port; and
a sixth multiplexer comprising two inputs coupled to an output of the fourth synchronization logic and a second bypass path coupled to the first primary port and an output coupled to the second primary port.
16. The memory module of claim 13 , wherein the data buffer component further comprises a passive asynchronous bypass path directly coupled between the first primary port and the second primary port.
17. The memory module of claim 13 , wherein the data buffer component is to couple to point-to-point data-links of a memory channel, wherein the point-to-point data-links do not connect to all other memory modules connected to a memory controller to which the memory module is connected.
18. The memory module of claim 13 , further comprising a plurality of dynamic random access memory (DRAM) devices disposed at respective device sites, wherein the data buffer component is to couple to point-to-point data-links of a memory channel, wherein the point-to-point data-links are at least one of point-to-point (P-to-P) links or point-to-two-points (P-to-2P) links.
19. The memory module of claim 13 , further comprising:
eighteen dynamic random access memory (DRAM) devices disposed at the respective device sites;
nine data buffer components coupled to the eighteen DRAM devices, each of the nine data buffer components being coupled to a pair of the eighteen DRAM devices, wherein the nine data buffer components includes the data buffer component; and
a command and address (CA) buffer component coupled to the eighteen DRAM devices.
20. The memory module of claim 13 , further comprising:
a plurality of dynamic random access memory (DRAM) devices disposed at respective of device sites; and
a plurality of data buffer components coupled to the plurality of DRAM devices.