IP Library Granted Patent US 9,658,794
Granted Patent B2
US 9,658,794 · App. 14/708,110 · Granted May 23, 2017

Two stage memory allocation using a cache

Inventor: Xiangyang Zhang (San Jose, CA)
Assignee: SONICWALL INC.
G06F3/0644G06F3/0604G06F3/0631G06F3/0673
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Quick Facts
Patent No.
US 9,658,794
App. No.
14/708,110
Filed
May 8, 2015
Granted
May 23, 2017
Kind
B2
Art Unit
2133
USPC
711/171
Abstract

The presently claimed invention manages memory in a multi-processor system. The presently claimed invention may use a combination of global and local locks when allocating memory and de-allocating memory in a multi-processor system. A method consistent with the presently claimed invention may first receive an allocation of a first memory space in the system memory of a multi-core processing system. The allocation of the first memory space may globally locks the first memory space where the memory space may administered by a software module using one or more local locks.

Claims (81)

1. A method for allocating memory on a multi-core processing system, the method comprising:

receiving a first allocation of a first memory space of system memory of the multi-core processing system at a first software module, wherein the first allocation of the first memory space globally locks the first memory space;

receiving a first request for locally locking a first portion of memory, wherein the first portion of memory is of a size that corresponds to a memory size that spans a range of memory addresses from a first starting memory address;

locking the first portion of memory with a first local lock, wherein the first portion of memory includes memory addresses in the first memory space; and

storing the first starting memory address in a first entry of a data structure.

2. The method of claim 1 , further comprising:

receiving a second request for locally locking a second portion of memory, wherein the second portion of memory corresponds to the size of the first portion of memory that spans a range of memory addresses from a second starting memory address;

locking the second portion of memory with a second local lock, wherein the second portion of memory includes memory addresses in the second memory space;

storing the second starting memory address in a second entry in the data structure;

receiving a third request for locally locking a third portion of memory, wherein the third portion of memory corresponds to the size of the first portion of memory that spans a range of memory addresses from a third starting memory address,

locking the third portion of memory with a third local lock, wherein the third portion of memory includes memory addresses in the third memory space; and

storing the third starting memory address in a third entry in the data structure.

3. The method of claim 2 , wherein:

the first entry in the data structure includes a pointer to the first starting memory address;

the second entry in the data structure includes a pointer to the second starting memory address; and

the third entry in the data structure includes a pointer to the third starting memory address.

4. The method of claim 2 , wherein:

the first portion of memory is exclusively accessed by a first thread executed by one or more processors at the multi-core processor;

the second portion of memory is exclusively accessed by a second thread executed by one or more processors at the multi-core processor; and

the third portion of memory is exclusively accessed by a third thread executed by one or more processors at the multi-core processor.

5. The method of claim 3 , further comprising:

receiving an indication that identifies the first local lock, the second local lock, or the third local lock is no longer required;

unlocking the local lock identified by the indication; and

deleting an entry in the data structure identified by the indication.

6. The method of claim 3 , wherein:

the data structure is a linked list,

the first entry in the data structure includes a pointer to the second entry in the data structure; and

the second entry in the data structure includes a pointer to the third entry in the data structure.

7. The method of claim 3 , further comprising:

receiving an allocation of a second memory space of the system memory of the computer system at the first software module, wherein the allocation of the second memory space globally locks the second memory space; and

receiving a fourth request for locally locking a portion of memory, wherein the size of the fourth portion of memory corresponds to the size of the first portion of memory that spans a range of memory addresses from a fourth starting memory address.

8. The method of claim 7 , further comprising:

receiving an indication that the fourth local lock is no longer required;

unlocking the local lock associated with the fourth local lock; and

unlocking the global lock locking the second memory space of the system memory.

9. The method of claim 2 , wherein the size of the first, the second, and the third portions of memory are equal and correspond to a size of memory relating to a process performed by an application program executed by one or more cores of the multi-core processor.

10. The method of claim 9 , wherein the application program process corresponds to at least one of storing data packets, a secure socket layer session, managing an endpoint of an Internet protocol security tunnel, network address translation object management, dynamic firewall policy management, and managing a session in a firewall.

11. A non-transitory computer readable storage medium having embodied thereon a program executable by a processor for performing a method for allocating memory on a multi-core processing system, the method comprising:

receiving a first allocation of a first memory space of system memory of the multi-core processing system, wherein the first allocation of the first memory space globally locks the first memory space;

receiving a first request for locally locking a first portion of memory, wherein the first portion of memory is of a size that corresponds to a memory size that spans a range of memory addresses from a first starting memory address;

locking the first portion of memory with a first local lock, wherein the first portion of memory includes memory addresses in the first memory space; and

storing the first starting memory address in a first entry in a data structure.

12. The non-transitory computer readable storage medium of claim 11 , the program further executable to:

receive a second request for locally locking a second portion of memory, wherein the second portion of memory corresponds to the size of the first portion of memory that spans a range of memory addresses from a second starting memory address;

lock the second portion of memory with a second local lock, wherein the second portion of memory includes memory addresses in the second memory space;

store the second starting memory address in a second entry in the data structure;

receive a third request for locally locking a third portion of memory, wherein the third portion of memory corresponds to the size of the first portion of memory that spans a range of memory addresses from a third starting memory address,

lock the third portion of memory with a third local lock, wherein the third portion of memory includes memory addresses in the third memory space; and

store the third starting memory address in a third entry in the data structure.

13. The non-transitory computer readable storage medium of claim 12 , wherein:

the first entry in the data structure includes a pointer to the first starting memory address;

the second entry in the data structure includes a pointer to the second starting memory address; and

the third entry in the data structure includes a pointer to the third starting memory address.

14. The non-transitory computer readable storage medium of claim 12 , wherein:

the first portion of memory is exclusively accessed by a first thread executed by one or more processors at the multi-core processor;

the second portion of memory is exclusively accessed by a second thread executed by one or more processors at the multi-core processor; and

the third portion of memory is exclusively accessed by a third thread executed by one or more processors at the multi-core processor.

15. The non-transitory computer readable storage medium of claim 13 , the program further executable to:

receive an indication that identifies the first local lock, the second local lock, or the third local lock is no longer required;

unlock the local lock identified by the indication; and

delete an entry in the data structure identified by the indication.

16. The non-transitory computer readable storage medium of claim 13 , wherein:

the data structure is a linked list,

the first entry in the data structure includes a pointer to the second entry in the data structure; and

the second entry in the data structure includes a pointer to the third entry in the data structure.

17. The non-transitory computer readable storage medium of claim 13 , the program further executable to:

receive an allocation of a second memory space of the system memory of the computer system, wherein the allocation of the second memory space globally locks the second memory space; and

receive a fourth request for locally locking a portion of memory, wherein the size of the fourth portion of memory corresponds to the size of the first portion of memory that spans a range of memory addresses from a fourth starting memory address.

18. The non-transitory computer readable storage medium of claim 17 , the program further executable to:

receive an indication that a fourth local lock is no longer required;

unlock the local lock associated with the fourth local lock; and

unlock the global lock locking the second memory space of the system memory.

19. The non-transitory computer readable storage medium of claim 12 , wherein the size of the first, the second, and the third portions of memory are equal and correspond to a size of memory relating to a process performed by an application program executed by one or more cores of the multi-core processor.

20. The non-transitory computer readable storage medium of claim 19 , wherein the application program process corresponds to at least one of storing data packets, a secure socket layer session, managing an endpoint of an Internet protocol security tunnel, network address translation object management, dynamic firewall policy management, and managing a session in a firewall.

21. An apparatus for allocating memory, the apparatus comprising:

a memory; and

multiple processors, wherein at least one of the one or more multiple processors executes instructions out of the memory, wherein the at least one or more processors:

receives a first allocation of a first memory space of system memory of the multi-core processing system at a first software module, the first allocation of the first memory space globally locks the first memory space;

receives a first request for locally locking a first portion of memory, the first portion of memory is of a size that corresponds to a memory size that spans a range of memory addresses from a first starting memory address;

locks the first portion of memory with a first local lock, wherein the first portion of memory includes memory addresses in the first memory space; and

stores the first starting memory address in a first entry of a data structure.

Assignments (24)
SECURITY INTEREST Recorded Jul 9, 2026
From: SONICWALL US HOLDINGS INC.; SONICWALL INC.; BANYAN SECURITY, INC.
To: UBS AG, STAMFORD BRANCH
Reel/Frame 075961/0674 →
SECURITY INTEREST Recorded Jul 9, 2026
From: SONICWALL US HOLDINGS INC.; SONICWALL INC.; BANYAN SECURITY, INC.
To: UBS AG, STAMFORD BRANCH
Reel/Frame 075961/0907 →
FIRST LIEN IP SUPPLEMENT Recorded Jun 30, 2025
From: SONICWALL US HOLDINGS INC.
To: UBS AG, STAMFORD BRANCH, AS COLLATERAL AGENT
Reel/Frame 071777/0641 →
RELEASE OF SECOND LIEN SECURITY INTEREST IN PATENTS RECORDED AT RF 046321/0393 Recorded Jun 16, 2025
From: UBS AG, STAMFORD BRANCH, AS COLLATERAL AGENT
To: SONICWALL US HOLDINGS INC.
Reel/Frame 071625/0887 →
FIRST LIEN PATENT SECURITY AGREEMENT Recorded Jun 7, 2018
From: SONICWALL US HOLDINGS INC.
To: UBS AG, STAMFORD BRANCH, AS COLLATERAL AGENT
Reel/Frame 046321/0414 →
SECOND LIEN PATENT SECURITY AGREEMENT Recorded Jun 7, 2018
From: SONICWALL US HOLDINGS INC.
To: UBS AG, STAMFORD BRANCH, AS COLLATERAL AGENT
Reel/Frame 046321/0393 →
RELEASE OF FIRST LIEN SECURITY INTEREST IN PATENTS RECORDED AT R/F 040581/0850 Recorded May 22, 2018
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
To: QUEST SOFTWARE INC. (F/K/A DELL SOFTWARE INC.); AVENTAIL LLC
Reel/Frame 046211/0735 →
CHANGE OF NAME Recorded Nov 29, 2017
From: DELL SOFTWARE INC.
To: QUEST SOFTWARE INC.
Reel/Frame 044551/0553 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE PREVIOUSLY RECORDED AT REEL: 040587 FRAME: 0624. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 28, 2017
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: QUEST SOFTWARE INC. (F/K/A DELL SOFTWARE INC.); AVENTAIL LLC
Reel/Frame 044811/0598 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 041073 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE INTELLECTUAL PROPERTY ASSIGNMENT.. Recorded Apr 5, 2017
From: QUEST SOFTWARE INC.
To: SONICWALL US HOLDINGS INC.
Reel/Frame 042168/0114 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Jan 23, 2017
From: QUEST SOFTWARE INC.
To: SONICWALL US HOLDINGS, INC.
Reel/Frame 041073/0001 →
SECOND LIEN PATENT SECURITY AGREEMENT Recorded Nov 10, 2016
From: DELL SOFTWARE INC.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040587/0624 →
FIRST LIEN PATENT SECURITY AGREEMENT Recorded Nov 9, 2016
From: DELL SOFTWARE INC.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040581/0850 →
RELEASE OF SECURITY INTEREST Recorded Oct 31, 2016
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: AVENTAIL LLC; DELL PRODUCTS, L.P.; DELL SOFTWARE INC.
Reel/Frame 040521/0467 →
RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040039/0642) Recorded Oct 31, 2016
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
To: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.
Reel/Frame 040521/0016 →
RELEASE OF REEL 036502 FRAME 0291 (NOTE) Recorded Sep 14, 2016
From: BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: DELL SOFTWARE INC.; DELL PRODUCTS L.P.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040027/0637 →
RELEASE OF REEL 036502 FRAME 0237 (TL) Recorded Sep 14, 2016
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: DELL SOFTWARE INC.; DELL PRODUCTS L.P.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040028/0088 →
SECURITY AGREEMENT Recorded Sep 14, 2016
From: AVENTAIL LLC; DELL PRODUCTS, L.P.; DELL SOFTWARE INC.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040030/0187 →
SECURITY AGREEMENT Recorded Sep 14, 2016
From: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 040039/0642 →
RELEASE OF REEL 036502 FRAME 0206 (ABL) Recorded Sep 13, 2016
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: DELL SOFTWARE INC.; DELL PRODUCTS L.P.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040017/0204 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT (TERM LOAN) Recorded Aug 27, 2015
From: DELL PRODUCTS L.P.; DELL SOFTWARE INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 036502/0237 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT (NOTES) Recorded Aug 27, 2015
From: DELL PRODUCTS L.P.; DELL SOFTWARE INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 036502/0291 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT (ABL) Recorded Aug 27, 2015
From: DELL PRODUCTS L.P.; DELL SOFTWARE INC.; WYSE TECHNOLOGY, L.L.C.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 036502/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2015
From: ZHANG, XIANGYANG
To: DELL SOFTWARE, INC.
Reel/Frame 035633/0913 →
Continuity (1)
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