Speculation control for improving transaction success rate, and instruction therefor
Throttling instruction execution in a transaction operating in a processor configured to execute memory instructions out-of-order in a pipelined processor, wherein memory instructions are instructions for accessing operands in memory is provided. Included is executing, by the processor, instructions of a transaction comprising determining whether the transaction is in throttling mode and based on the transaction being in throttling mode, executing memory instructions in-program-order. Also included is based on the transaction not-being in throttling mode, executing memory instructions out-of-program order.
1. A computer system for throttling instruction execution in a transaction operating in a processor configured to execute memory instructions out-of-order in a pipelined processor, wherein memory instructions are instructions for accessing operands in memory, the computer system comprising:
a memory;
a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
executing, by the processor, instructions of a transaction comprising:
executing non-memory instructions without engaging speculation throttling, wherein speculation throttling reduces the number of speculative transactional executions;
identifying a first set of memory instructions within the transaction, wherein the memory instructions must be executed in a particular order;
based on identifying a first set of memory instructions within the transaction, engaging speculation throttling;
identifying a second set of memory instructions within the transaction, wherein the memory instructions must be executed out-of-program order; and
based on identifying a second set of memory instructions within the transaction, executing the second set of memory instructions without engaging speculation throttling.
2. The computer system according to claim 1 , further comprising:
determining whether a position of the memory instructions within the processor pipeline is within a threshold distance of being executed; and
executing memory instructions engaging speculation throttling based on the memory instructions being not-speculative relative to resolution of older branch instructions.
3. The computer system according to claim 2 , wherein the determined memory instructions within the processor pipeline is within a threshold distance of being executed consist of at least one of memory instructions that are not further than a predefined number of instructions from completion, memory instructions that are not further than a predefined number of branches from completion, and memory instructions that are not further than a predefined number of unresolved branches from completion.
4. The computer system according to claim 2 , wherein the determined memory instructions within the processor pipeline is within a threshold distance of being executed consist of memory instructions that are next in a queue to be completed.
5. The computer system according to claim 1 , further comprising: executing a throttling mode setting instruction, the executing causing an instruction defined value to be set as a throttling mode value to indicate throttling mode.
6. The computer system according to claim 1 where in the throttling mode is engaged by a hardware or by a program.
7. The computer system according to claim 6 , wherein the hardware or program comprises at least one of a library, a middleware, an operating system, a hypervisor, a firmware, a dynamic optimization component, a millicode, or a hardware responsive to dynamic failure pattern or counts in a system.
8. A computer program product for throttling instruction execution in a transaction operating in a processor configured to execute memory instructions out-of-order in a pipelined processor, wherein memory instructions are instructions for accessing operands in memory, the computer program product comprising
a computer readable storage non-transitory medium readable by a processing circuit and storing instruction instructions for execution by the processing circuit for performing a method comprising:
executing, by the processor, instructions of a transaction comprising:
executing non-memory instructions without engaging speculation throttling, wherein speculation throttling reduces the number of speculative transactional executions;
identifying a first set of memory instructions within the transaction, wherein the memory instructions must be executed in a particular order;
based on identifying a first set of memory instructions within the transaction, engaging speculation throttling;
identifying a second set of memory instructions within the transaction, wherein the memory instructions must be executed out-of-program order; and
based on identifying a second set of memory instructions within the transaction, executing the second set of memory instructions without engaging speculation throttling.
9. The computer program product according to claim 8 , further comprising:
determining whether a position of the memory instructions within the processor pipeline is within a threshold distance of being executed; and
executing memory instructions engaging speculation throttling based on the memory instructions being not-speculative relative to resolution of older branch instructions.
10. The computer program product according to claim 9 , wherein the determined memory instructions within the processor pipeline is within a threshold distance of being executed consist of at least one of memory instructions that are not further than a predefined number of instructions from completion, memory instructions that are not further than a predefined number of branches from completion, and memory instructions that are not further than a predefined number of unresolved branches from completion.
11. The computer program product according to claim 9 , wherein the determined memory instructions within the processor pipeline is within a threshold distance of being executed consist of memory instructions that are next in a queue to be completed.
12. The computer program product according to claim 8 , further comprising: executing a throttling mode setting instruction, the executing causing an instruction defined value to be set as a throttling mode value to indicate throttling mode.
13. The computer program product according to claim 8 , where in the throttling mode is engaged by a hardware or by a program.
14. The computer program product according to claim 13 , wherein the hardware or program comprises at least one of a library, a middleware, an operating system, a hypervisor, a firmware, a dynamic optimization component, a millicode, or a hardware responsive to dynamic failure pattern or counts in a system.