Gate driver circuit, display apparatus having the same, and gate driving method
A gate driver, a display apparatus having the same, and a gate driving method are provided. The display apparatus includes a plurality of pixels, a data driver circuit, and a gate driver circuit. The gate driver circuit includes M groups of gate channels. Each of the M groups of gate channels includes a control circuit and an output buffer. The control circuit receives a power supply voltage from a power supply circuit and generates a modulated supply voltage. The output buffer is connected to the control circuit, the output buffer is powered by the modulated supply voltage to output a gate signal to a gate line of the display panel, wherein a driving pulse of the gate signal is shaped during a charge period according to the modulated supply voltage, and the shape of the driving pulse of the gate signal is maintained during a pre-charge period.
1. A gate driver circuit for driving a display panel, comprising:
M groups of gate channels, M being an integer greater than 1, wherein each of the M groups of gate channels comprises:
a control circuit receiving a power supply voltage from a power supply circuit and generating a modulated supply voltage; and
an output buffer connected to the control circuit, the output buffer powered by the modulated supply voltage and receiving an input signal, so as to output a gate signal to a gate line of the display panel, wherein a driving pulse of the gate signal is shaped during a charge period according to the modulated supply voltage, and the shape of the driving pulse of the gate signal is maintained at a preset level during a pre-charge period, wherein the length of the pre-charge period is adjusted according to the number of scan lines.
2. The gate driver circuit according to claim 1 , wherein the control circuits in the M groups of gate channels modulate the power supply voltage so that each of the driving pulses of the gate signals is maintained at the preset level during the pre-charge period.
3. The gate driver circuit according to claim 1 , wherein the control circuits in the M groups of gate channels are independent from each other, and each of the modulated supply voltages is generated independently by each of the control circuits in the M groups of gate channels.
4. The gate driver circuit according to claim 1 , wherein the control circuits and the output buffers of each of the M groups of gate channels are manufactured on a same chip.
5. The gate driver circuit according to claim 1 , wherein the control circuits of each of the M groups of gate channels are integrated in the corresponding output buffers.
6. A display apparatus, comprising:
a plurality of pixels receiving data signals in response to gate signals and displaying an image corresponding to the data signals;
a data driver circuit applying the data signals to the pixels; and
a gate driver circuit sequentially applying the gate signals to the pixels according to modulated supply voltages, the gate driver circuit comprising:
M groups of gate channels, M being an integer greater than 1, wherein each of the M groups of gate channels comprises:
a control circuit receiving a power supply voltage from a power supply circuit and generating a modulated supply voltage; and
an output buffer connected to the control circuit, the output buffer powered by the modulated supply voltage and receiving an input signal, so as to output a gate signal to a gate line of the display panel, wherein a driving pulse of the gate signal is shaped during a charge period according to the modulated supply voltage, and the shape of the driving pulse of the gate signal is maintained at a preset level during a pre-charge period, wherein the length of the pre-charge period is adjusted according to the number of scan lines.
7. The display apparatus according to claim 6 , wherein the control circuits in the M groups of gate channels modulate the power supply voltage so that each of the driving pulses of the gate signals is maintained at the preset level during the pre-charge period.
8. The display apparatus according to claim 6 , wherein the control circuits in the M groups of gate channels are independent from each other, and each of the modulated supply voltages is generated independently by each of the control circuits in the M groups of gate channels.
9. The display apparatus according to claim 6 , wherein the control circuits and the output buffers of each of the M groups of gate channels are manufactured on a same chip.
10. The display apparatus circuit according to claim 6 , wherein the control circuits of each of the M groups of gate channels are integrated in the corresponding output buffers.
11. A gate driving method for a display panel, the gate driving method comprising:
dividing a plurality of gate channels into M groups, M being an integer greater than 1;
for each of the M groups of gate channels:
receiving, by a control circuit, a power supply voltage from a power supply circuit and generating a modulated supply voltage; and
outputting, by an output buffer powered by the modulated supply voltage, a gate signal to a gate line of the display panel according to an input signal and the modulated supply voltage, wherein a driving pulse of the gate signal is shaped during a charge period according to the modulated supply voltage, and the shape of the driving pulse of the gate signal is maintained at a preset level during a pre-charge period, wherein the length of the pre-charge period is adjusted according to the number of scan lines.
12. The gate driving method according to claim 11 , wherein the power supply voltage is modulated by the control circuits in the M groups of gate channels so that each of the driving pulses of the gate signals is maintained at the preset level during the pre-charge period.
13. The gate driving method according to claim 11 , wherein the control circuits in the M groups of gate channels are independent from each other, and each of the modulated supply voltages is generated independently by each of the control circuits in the M groups of gate channels.
14. The gate driving method according to claim 11 , wherein the control circuits and the output buffers of each of the M groups of gate channels are manufactured on a same chip.
15. The gate driving method according to claim 11 , wherein the control circuits of each of the M groups of gate channels are integrated in the corresponding output buffers.