Method and circuit for controlling programming current in a non-volatile memory array
A memory device having: a cross-point memory array; a current supply circuit adapted to supply a programming current to a selected row line of the array during a programming operation to change the resistive state of a selected memory cell coupled between the selected row line and a selected column line of the array; a leakage current detection circuit coupled to the column lines except the selected column line and adapted to detect leakage currents during the programming operation; and a current limit generation circuit adapted to generate a current limit based on the sum of the leakage currents and on a reference current, and to supply the current limit to the current supply circuit to limit the programming current.
1. A memory device comprising:
a cross-point memory array comprising a plurality of row lines, a plurality of column lines and a plurality of memory cells arranged in rows and columns, each memory cell comprising a non-volatile programmable resistive element coupled between a corresponding one of the row lines and a corresponding one of the column lines;
a current supply circuit adapted to supply a programming current to a selected one of the row lines during a programming operation to change the resistive state of a selected memory cell coupled between the selected row line and a selected one of the column lines;
a leakage current detection circuit coupled to the plurality of column lines except the selected column line and adapted to detect leakage currents during said programming operation; and
a current limit generation circuit adapted to generate a current limit based on the sum of the leakage currents and on a reference current, and to supply said current limit to the current supply circuit to limit said programming current.
2. The memory device of claim 1 , wherein the current limit generation circuit is adapted to generate the current limit by adding the sum of the leakage currents to the reference current, wherein the reference current represents the programming current to be applied to the selected memory cell.
3. The memory device of claim 1 , wherein the current supply circuit comprises a voltage regulator for controlling a first voltage level applied to the selected row line.
4. The memory device of claim 3 , wherein the voltage regulator comprises a first transistor coupled to the selected row line and having its control node coupled to the output of a comparator adapted to compare the voltage on the selected row line with a reference voltage at the first voltage level.
5. The memory device of claim 1 , wherein the current supply circuit comprises a current mirror having a reference branch coupled to receive the current limit and a further branch coupled to the selected row line.
6. The memory device of claim 1 , wherein the current supply circuit comprises a further comparator adapted to compare a first voltage level generated based on the current limit with a second voltage level generated based on the programming current, and to control the programming current based on said comparison.
7. The memory device of claim 1 , wherein the leakage current detection circuit comprises a voltage regulator for controlling a second voltage level applied to the column lines except the selected column line.
8. The memory device of claim 1 , wherein the current limit generation circuit comprises:
a first current mirror having a reference branch coupled to receive the sum of the leakage currents and a further branch;
a second current mirror having a reference branch coupled to receive the reference current and a further branch, wherein the further branches of the first and second current mirrors are coupled to an output line of the current limit generation circuit providing the current limit.
9. The memory device of claim 1 , comprising:
one or more further current supply circuits adapted to supply a programming current to one or more further selected row lines during the programming operation to change the resistive state of one or more of the memory cells coupled to the selected column line; and
a division circuit adapted to divide the sum of the leakage currents by the number of current supply circuits.
10. The memory device of claim 1 , wherein the non-volatile programmable resistive element is one of:
an OxRAM device;
a PCM device; and
an MRAM device.
11. The memory device of claim 1 , wherein each memory cell further comprises a two-way selection device coupled in series with the non-volatile programmable resistive element and adapted to conduct above a threshold voltage.
12. A method of limiting a programming current in a cross-point non-volatile memory array comprising a plurality of row lines, a plurality of column lines and a plurality of memory cells arranged in rows and columns, each memory cell comprising a non-volatile programmable resistive element coupled between a corresponding one of the row lines and a corresponding one of the column lines, the method comprising:
supplying, by a current supply circuit, a programming current to a selected one of the row lines during a programming operation to change the resistive state of a selected memory cell coupled between the selected row line and a selected one of the column lines;
detecting, by a leakage current detection circuit coupled to the plurality of column lines except the selected column line, leakage currents during said programming operation;
generating, by a current limit generation circuit, a current limit based on the sum of the leakage currents and on a reference current; and
supplying said current limit to the current supply circuit to limit said programming current.