IP Library Granted Patent US 9,673,158
Granted Patent B2
US 9,673,158 · App. 14/630,265 · Granted Jun 6, 2017

Formation of connectors without UBM

Inventors: Tsung-Ding Wang (Tainan, TW); Hung-Jen Lin (Tainan, TW); Chien-Hsun Lee (Chu-tung Town, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L24/11H01L21/561H01L21/563H01L23/3192H01L24/13H01L24/18H01L24/81H01L23/293H01L24/16H01L2224/02379H01L2224/0391H01L2224/0401H01L2224/05548H01L2224/05567H01L2224/05647H01L2224/10126H01L2224/1131H01L2224/11334H01L2224/11515H01L2224/11849H01L2224/13022H01L2224/13023H01L2224/16225H01L2224/16227H01L2224/73204H01L2224/81024H01L2224/81815H01L2224/94H01L2924/00014
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Quick Facts
Patent No.
US 9,673,158
App. No.
14/630,265
Granted
Jun 6, 2017
Kind
B2
Abstract

A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer.

Claims (49)

1. A method comprising:

forming a conductive feature over a substrate;

forming a dielectric layer covering the conductive feature;

forming an opening in the dielectric layer to reveal a portion of the conductive feature;

disposing a compound into the opening, wherein the compound comprises a flux and a polymer;

placing a solder ball over the compound; and

reflowing the solder ball to form a solder region, wherein the solder region contacts the conductive feature, and after the reflowing, the compound comprises a bottom surface spaced apart from a top surface of the conductive feature by the dielectric layer.

2. The method of claim 1 , wherein after the reflowing, the compound comprises a first portion contacting a sidewall of a mid-section of the solder ball, and the first portion comprises a bottom surface in contact with a top surface of the dielectric layer.

3. The method of claim 2 , wherein after the reflowing, the compound further comprises a second portion in a recess of the dielectric layer, wherein the second portion is physically separated from the first portion.

4. The method of claim 1 , wherein after the reflowing, the compound comprises:

a first portion in a recess of the dielectric layer, and in a region formed by a bottom surface of the solder region, a sidewall of the dielectric layer, and a top surface of the conductive feature; and

a second portion over a top surface of the dielectric layer, wherein the second portion contacts a mid-section of the solder region.

5. The method of claim 1 further comprising bonding a package component to the solder region, wherein between the reflowing and the bonding, no flux clean step is performed.

6. The method of claim 5 , wherein the package component is selected from the group consisting essentially of a device die, a package substrate, and a printed circuit board (PCB).

7. The method of claim 5 further comprising disposing an underfill between the dielectric layer and the package component, wherein the underfill is in physical contact with the compound.

8. The method of claim 5 further comprising disposing an underfill between the dielectric layer and the package component, wherein the underfill is physically separated from the compound.

9. A method comprising:

forming a first package component comprising:

forming a conductive feature;

forming a dielectric layer over the conductive feature;

forming a solder region over the conductive feature, wherein a portion of the solder region extends into the dielectric layer; and

dispensing a compound comprising a first portion in contact with the conductive feature and the dielectric layer, wherein the compound comprises flux and a polymer, and the first portion of the compound comprises a bottom surface spaced apart from a top surface of the conductive feature by the dielectric layer; and

bonding the first package component to a second package component

wherein after the bonding, the second package component is bonded to the solder region.

10. The method of claim 9 further comprising disposing an underfill between the dielectric layer and the second package component, wherein the underfill is in physical contact with the compound.

11. The method of claim 9 further comprising:

before the bonding, forming the dielectric layer covering the conductive feature;

forming an opening in the dielectric layer to reveal a portion of the conductive feature; and

disposing the compound into the opening.

12. The method of claim 11 further comprising:

placing a solder ball over the compound; and

reflowing the solder ball to form a solder region, wherein the solder region contacts the conductive feature.

13. The method of claim 12 , wherein the reflowing separates the compound into the first portion and a second portion physically separated from the first portion, wherein the second portion is in a recess of the dielectric layer.

14. A method comprising:

forming a passivation layer comprising a portion over a metal pad;

forming a post-passivation interconnect (PPI) electrically coupled to the metal pad, wherein the PPI comprises at least a portion over the metal pad and the passivation layer;

forming a polymer layer over the PPI;

forming an opening in the polymer layer;

filling a compound into the opening, wherein the compound is in physical contact with the PPI, and the compound comprises a flux and a polymer, and wherein the polymer layer is a surface layer of a wafer, and in the filling the compound, the compound is applied as a blanket layer over the wafer, and comprises:

first portions in a plurality of openings in the polymer layer; and

second portions interconnecting the first portions into a continuous compound;

placing a solder ball on the compound; and

reflowing the solder ball to form a solder region joined with the PPI.

15. The method of claim 14 further comprising bonding a package component to the solder region, wherein the package component is selected from the group consisting essentially of a device die, a package substrate, and a printed circuit board (PCB), and wherein between the reflowing and the bonding, no flux clean step is performed.

16. The method of claim 14 , wherein after the reflowing, the compound extends into a region between the PPI, the polymer layer, and the solder region.

17. The method of claim 1 , wherein the compound is disposed as separate portions in a plurality of openings in the dielectric layer, and the separate portions are not interconnected into a continuous layer.

18. The method of claim 1 , wherein the compound is disposed as comprising first portions in a plurality of openings in the dielectric layer, and second portions interconnecting the first portions into a continuous layer.

19. The method of claim 1 , wherein the dielectric layer is a surface layer of a wafer, and the compound is applied as a blanket layer over the wafer.

20. The method of claim 9 , wherein the dielectric layer is a surface layer of a wafer, and the compound is disposed as a blanket layer over the wafer.

Assignments (1)
CORRECTIVE ASSIGNMENT TO CORRECT THE 3RD INVENTOR'S NAME PREVIOUSLY RECORDED AT REEL: 026984 FRAME: 0714. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT . Recorded Mar 27, 2017
From: WANG, TSUNG-DING; LIN, HUNG-JEN; LEE, CHIEN-HSUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 042154/0484 →
Continuity (2)
Division 13247529 · Sep 28, 2011
Related Publication 20150171037A1 · Jun 18, 2015