Semiconductor device including capacitor and method of fabricating the same
A semiconductor device includes a lower electrode on a lower structure, a dielectric layer conformally covering a surface of the lower electrode, an upper electrode conformally covering a surface of the dielectric layer, and a barrier layer on the upper electrode. The barrier layer and the upper electrode define a space on a sidewall of the lower electrode.
1. A semiconductor device comprising:
a lower electrode on a lower structure;
a support pattern on a portion of a sidewall of the lower electrode;
a dielectric layer conformally covering a surface of the lower electrode;
an upper electrode conformally covering a surface of the dielectric layer; and
a barrier layer on the upper electrode,
wherein the barrier layer and the upper electrode define a space on the sidewall of the lower electrode.
2. The semiconductor device of claim 1 , further comprising:
a capping layer covering the barrier layer on the lower structure.
3. The semiconductor device of claim 2 , further comprising:
a middle layer between the barrier layer and the capping layer, the middle layer including a titanium-silicon nitride (TiSiN) layer.
4. The semiconductor device of claim 1 , wherein
the upper electrode and the barrier layer include a same material,
the upper electrode has a tensile stress, and
the barrier layer has a compressive stress.
5. The semiconductor device of claim 1 , wherein the barrier layer is a titanium nitride layer.
6. A semiconductor device comprising:
a lower electrode on a lower structure;
a first support pattern on a first sidewall of the lower electrode;
a dielectric layer conformally covering the lower electrode and the first support pattern;
an upper electrode conformally covering the dielectric layer; and
a barrier layer on the upper electrode to cover a top surface of the lower electrode,
wherein the first support pattern, the first sidewall of the lower electrode, and the lower structure define a first space under the first support pattern and surrounded by the upper electrode.
7. The semiconductor device of claim 6 , wherein
the lower electrode includes,
a first lower electrode part below the first support pattern, and
a second lower electrode part above the first support pattern; and
the upper electrode includes,
a first upper electrode part covering the first lower electrode part, and
a second upper electrode part covering the second lower electrode part.
8. The semiconductor device of claim 7 , wherein the barrier layer contacts a portion of the upper electrode covering a sidewall of the first support pattern and extends onto a top surface of the lower structure.
9. The semiconductor device of claim 8 , wherein
the first upper electrode part includes a first vertical portion covering a sidewall of the first lower electrode part, a first top portion under the first support pattern and a first bottom portion on the lower structure, and
the first vertical portion, the first top portion, the first bottom portion and the barrier layer define a second space.
10. The semiconductor device of claim 8 , wherein
the first support pattern, the second lower electrode part, and the barrier layer define a third space on the first support pattern, and
the upper electrode and the barrier layer surround the third space.
11. The semiconductor device of claim 10 , wherein
the second upper electrode part includes a second vertical portion covering a sidewall of the second lower electrode part, a second top portion under a second support portion and a second bottom portion on the first support pattern, and
the second vertical portion, the second top portion, the second bottom portion and the barrier layer define the third space.
12. The semiconductor device of claim 6 , wherein
a second sidewall of the lower electrode, the lower structure, and the barrier layer define a fourth space on the lower structure, and
the upper electrode and the barrier layer surround the fourth space.
13. The semiconductor device of claim 8 , wherein
the lower structure includes a cell region and a peripheral circuit region,
the lower electrode, the dielectric layer, the upper electrode, and the barrier layer are sequentially stacked on the lower structure of the cell region, and
the barrier layer extends onto the top surface of and covers the lower structure of the peripheral circuit region.
14. The semiconductor device of claim 6 , wherein
the upper electrode and the barrier layer include a same material,
the upper electrode has a tensile stress, and
the barrier layer has a compressive stress.
15. A semiconductor device comprising:
a lower electrode on a lower structure;
a support pattern on a portion of a sidewall of the lower electrode
a dielectric layer on the lower electrode;
an upper electrode on the dielectric layer; and
a barrier layer on the upper electrode, the barrier layer having an uppermost portion including titanium-silicon nitride (TiSiN).
16. The semiconductor device of claim 15 , further comprising:
a capping layer covering the barrier layer.
17. The semiconductor device of claim 15 , wherein
the upper electrode and the barrier layer include a same material,
the upper electrode has a tensile stress, and
the barrier layer has a compressive stress.
18. The semiconductor device of claim 15 , wherein a lower portion of the barrier layer includes titanium nitride.