IP Library › Granted Patent US 9,673,278
Granted Patent B2
US 9,673,278 · App. 14/820,547 · Granted Jun 6, 2017

Method of preventing drain and read disturbances in non-volatile memory device

Inventor: Chengcheng Wang (Shanghai, CN)
Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
H01L29/0847H01L29/6656H01L29/6659H01L29/66492H01L29/66659H01L29/7835H01L21/266H01L21/26513H01L21/26586H01L21/823425H01L27/11521
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Quick Facts
Patent No.
US 9,673,278
App. No.
14/820,547
Granted
Jun 6, 2017
Kind
B2
Abstract

A source-drain structure and method of manufacturing the same are disclosed. The source-drain structure includes a substrate containing a drain region and a source region. The drain region includes a lightly-doped ultra-shallow junction and a heavily-doped region, and a drain-substrate junction disposed in the vicinity of a junction between a side portion and a bottom portion of the lightly-doped ultra-shallow junction and the substrate, a plurality of impurity ions in the drain-substrate junction and a plurality of impurity ions in the lightly-doped ultra-shallow junction are opposite-conductivity type ions. The drain-substrate junction can smooth out the steep surface of the lightly-doped ultra-shallow junction to minimize the maximum electric field and reduce the ion flow close to the channel, and effectively reduce the inter-band tunneling hot electron effect.

Claims (17)

1. A method of manufacturing a source-drain structure, the method comprising:

forming a plurality of gate electrodes on a substrate;

forming a drain region and a source region;

forming a lightly-doped ultra-shallow junction comprising a plurality of one-conductivity type impurity ions in the drain region;

forming spacers on opposite sides of the gate electrodes;

performing a first opposite-conductivity type deep ion implantation comprising a plurality of impurity ions onto the lightly-doped ultra-shallow junction to form a drain-substrate junction in the vicinity of a junction between a side portion and a bottom portion of the lightly-doped ultra-shallow junction and the substrate, the drain-substrate junction comprising the plurality of impurity ions opposite the plurality of one-conductivity type impurity ions of the lightly-doped ultra-shallow junction; and

performing a heavily-doped ion implantation onto the lightly-doped ultra-shallow junction to form a heavily-doped drain region.

2. The method of claim 1 , wherein spacers on adjacent gate electrodes in a source region disposed between the adjacent gate electrodes are in contact with each other.

3. The method of claim 1 , wherein the first opposite-conductivity type deep ion implantation is performed at an angle of an ion beam in relation to a surface of the substrate in a range between 45 degrees and 85 degrees, an energy in a range between 10 keV and 50 keV.

4. The method of claim 1 , wherein the first opposite-conductivity type deep ion implantation is performed with a dose smaller than a dose of the heavily-doped ion implantation.

5. The method of claim 4 , wherein the dose of the heavily-doped ion implantation is in a range between 2E11 cm −2 and 2E13 cm −2 .

6. The method of claim 1 , further comprising, prior to forming the lightly-doped ultra-shallow junction in the drain region:

performing a self-aligned ion implantation comprising a plurality of first-conductivity type ions onto a portion of the substrate to form a self-aligned source region;

performing a second deep opposite-conductivity type ion implantation comprising a plurality of second ions opposite the plurality of first-conductivity type ions onto the formed self-aligned source region to form a source-substrate junction in the vicinity of a junction between a side portion and bottom portion of the self-aligned source region and the substrate.

7. The method of claim 6 , wherein performing the second deep opposite-conductivity type ion implantation comprises using an implantation angle between 45 degrees and 80 degrees in relation to a surface of the substrate, and an energy greater than an energy of the self-aligned ion implantation.

8. The method of claim 1 , wherein the heavily-doped drain region divides the lightly-doped ultra-shallow junction into a first junction region and a second junction region, and the heavily-doped drain region has a width smaller than a width of the first junction region or a width of the second junction region.

9. The method of claim 1 , wherein the drain-substrate junction comprises an edge curvature smaller than an edge curvature of the lightly-doped ultra-shallow junction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2015
From: WANG, CHENGCHENG
To: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Reel/Frame 036293/0353 →
Priority Claims (1)
CN 2014 1 0387740 · Aug 7, 2014 · national
Continuity (1)
Related Publication 20160043176A1 · Feb 11, 2016