Multiprocessor system with interrupt distributor
An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.
1. A multiprocessor system comprising:
a plurality of processors that includes a first processor and a second processor coupled to the first processor by a first bus;
a second bus coupled to the first bus;
a clock gating circuit directly coupled to the first processor and the second processor;
a first and second peripheral device coupled to the second bus; and
an interrupt distributor circuit coupled to the first bus and directly coupled to the first and second processor by an interrupt bus and directly coupled to the first and second peripheral device by a first and second peripheral interrupt line and directly coupled to the clock gating circuit, the interrupt distributor circuit being configured to:
receive interrupts on the first and the second peripheral interrupt lines, and in response to the interrupts received, distributes the interrupts between the first and the second processors and reduces power drawn by the plurality of processors by adjusting an operating frequency and operating voltage for the first and second processors.
2. The multiprocessor system of claim 1 , wherein the interrupt distributor circuit is configured to adjust the operating frequency and operating voltage of the first and the second processors by sending commands to the clock gating circuit, and wherein the interrupt distributor circuit is further configured to cause a reduction in the operating frequency and operating voltage that maintains a throughput for the multiprocessor system, as present before the reduction in the operating frequency and operating voltage is caused, by the interrupt distributor circuit being configured to distribute the interrupts using a priority that is based on availability of the plurality of processors to serve the interrupts.
3. The multiprocessor system of claim 1 further comprising a nonvolatile memory capable of storing interrupt service routines and coupled to the first bus.
4. The multiprocessor system of claim 1 further comprising an SRAM memory coupled to the first bus.
5. The multiprocessor system of claim 1 where the second bus is an Advanced Peripheral Bus.
6. The multiprocessor system of claim 1 where the first peripheral device is an analog to digital converter.
7. The multiprocessor system of claim 1 where the second peripheral device is a Universal Asynchronous Receiver/Transmitter (UART).
8. The multiprocessor system of claim 1 where the interrupt distributor statically tunes the operating frequency and voltage of the multiprocessor system.
9. The multiprocessor system of claim 1 , wherein the algorithm uses the number of processors in the plurality of processors, the operating frequency, the operating voltage, and a threshold voltage for turn on of transistors in the plurality of processors.
10. The multiprocessor system of claim 1 , wherein the interrupt distributor circuit adjusts the operating voltage and operating frequency for the plurality of processors while sharing interrupts received and distributing the interrupts received among the processors based on which one of the processors is the first available processor.
11. The multiprocessor system of claim 1 , wherein the algorithm is a power-aware scheduling algorithm configured to cause power-aware interrupt scheduling with priority constraints, whereby when multiple interrupts are received, the interrupts are scheduled according to a predefined interrupt priority.
12. The multiprocessor system of claim 3 wherein the nonvolatile memory is a multiport memory that has a separate port for each processor in the system and that stores interrupt service routines or interrupt handlers, and thereby allows each of the processors to handle the received interrupts.
13. The multiprocessor system of claim 4 where the SRAM memory is a multiport memory that has a separate port for each processor in the system.
14. The multiprocessor system of claim 9 , wherein the algorithm uses a velocity of saturation for the transistors.
15. The multiprocessor system of claim 14 , wherein the algorithm uses switching capacitances of the transistors at different values of the operating voltage.
16. The multiprocessor system of claim 14 , wherein the interrupt distributor circuit statically and dynamically tunes the operating voltage and operating frequency for the plurality of processors while sharing interrupts received and distributing the interrupts received among the processors based on their availability.
17. The multiprocessor system of claim 14 , wherein the interrupt distributor circuit adjusts the operating voltage and operating frequency for the plurality of processors while sharing interrupts received and distributing the interrupts received among the processors based on whether one of the processors is in idle mode and not busy, whereby the interrupt distributor circuit then routes a scheduled one of the interrupts to said one of the processors that is in idle mode and not busy.
18. The multiprocessor system of claim 14 , wherein the interrupt distributor circuit adjusts the operating voltage and operating frequency for the plurality of processors while sharing interrupts received and distributing the interrupts received among the processors based on which one of the processors is the first available processor.
19. The multiprocessor system of claim 14 , wherein the algorithm is a power-aware scheduling algorithm configured to cause power-aware interrupt scheduling with priority constraints, whereby when multiple interrupts are received, the interrupts are scheduled according to a predefined interrupt priority.
20. A method for making a multiprocessor system comprising:
providing a plurality of processors that includes a first processor and a second processor coupled to the first processor by a first bus;
providing a second bus coupled to the first bus;
providing a clock gating circuit directly coupled to the first processor and the second processor;
providing a first and second peripheral device coupled to the second bus; and
providing an interrupt distributor circuit coupled to the first bus and directly coupled to the first and second processor by an interrupt bus and directly coupled to the first and second peripheral device by a first and second peripheral interrupt line and directly coupled to the clock gating circuit, the interrupt distributor circuit configured to:
receive interrupts on the first and the second peripheral interrupt lines,
distribute, in response to an algorithm that is based upon the interrupts received and the number of processors in the plurality of processors, interrupts received on the peripheral interrupt lines between the first and the second processors, and
reduce power drawn by the plurality of processors during handling of the receive interrupts by adjusting, based upon the algorithm, an operating frequency and operating voltage for the first and second processors.