Semiconductor device and method of fabricating the same

1. A method of fabricating a semiconductor device, the method comprising:

sequentially forming a hard mask layer and a first sacrificial layer on a substrate;

forming an upper mandrel that includes at least first to third upper sub-mandrels on the first sacrificial layer, the first to third upper sub-mandrels each extending in a first direction and being spaced apart from each other in a second direction that intersects the first direction, a width of the first upper sub-mandrel in the second direction being smaller than widths of the second and third upper sub-mandrels in the second direction;

forming first spacers on both side walls of each of the first through third upper sub-mandrels;

removing the upper mandrel;

etching the first sacrificial layer using the first spacers as etching masks to form a lower mandrel that includes a plurality of lower sub-mandrels;

forming second spacers on both side walls of the lower sub-mandrels;

removing the lower mandrel;

patterning the hard mask layer and the substrate using the second spacers as etching masks to form a fin type pattern, the fin type pattern including first to tenth fins which extend alongside each other in the first direction and are spaced apart from each other in the second direction;

removing the first, second, fifth and eighth fins; and

forming a first gate electrode and a second gate electrode, the first gate electrode extending in the second direction to intersect the third, fourth, sixth and seventh fins, and the second gate electrode extending in the second direction to intersect the sixth, seventh, ninth and tenth fins while not intersecting the third and fourth fins, and being spaced apart from the first gate electrode in the first direction.

2. The method of claim 1 , wherein forming the upper mandrel comprises:

forming a second sacrificial layer on the first sacrificial layer; and

forming the upper mandrel by etching the second sacrificial layer.

3. The method of claim 2 , further comprising:

forming an anti-reflective layer between the first and second sacrificial layers.

4. The method of claim 1 , wherein a width of the second upper sub-mandrel is different than a width of the third upper sub-mandrel.

5. The method of claim 1 , wherein an interval between the first and second upper sub-mandrels is smaller than an interval between the second and third upper sub-mandrels.

6. The method of claim 1 , wherein the first spacer is formed by an atomic layer deposition process.

7. The method of claim 1 , wherein the lower sub-mandrels all have the same width in the second direction.

8. The method of claim 1 , further comprising:

forming an element isolation film after removing the first, second, fifth and eighth fins, wherein the third, fourth, sixth, seventh, ninth and tenth fin type patterns protrude above an upper surface of the element isolation film.

9. The method of claim 8 , wherein forming the element isolation film comprises:

forming a trench by etching the first and second fins; and

forming the element isolation film in the trench.

10. The method of claim 1 , wherein removing the first, second, fifth and eighth fins comprises:

forming a first trench by etching the first and second fins, forming a second trench by etching the fifth fin and forming a third trench by etching the eighth fin.

11. A method of fabricating a semiconductor device, the method comprising:

sequentially forming a hard mask layer and a first sacrificial layer on a substrate;

forming an upper mandrel that includes a plurality of upper sub-mandrels on the first sacrificial layer;

forming first spacers on side walls of upper sub-mandrels;

removing the upper mandrel;

etching the first sacrificial layer using the first spacers as etching masks to form a lower mandrel that includes a plurality of lower sub-mandrels;

forming second spacers on side walls of the lower sub-mandrels;

removing the lower mandrel;

forming first to sixth active fins which extend alongside one another in a first direction and are spaced apart from one another in a second direction that intersects the first direction by patterning the hard mask layer and the substrate using the second spacers as etching masks; and

forming a first gate electrode and a second gate electrode, the first gate electrode extending in the second direction to intersect the first to fourth active fins, and the second gate electrode extending in the second direction to intersect the third through sixth active fins, the second gate electrode not intersecting the first and second active fins, and being spaced apart from the first gate electrode in the first direction.

12. The method of claim 11 , wherein the plurality of upper sub-mandrels includes at least a first upper sub-mandrel and a second upper sub-mandrel, and

widths of the first and second upper sub-mandrels are different from each other.

13. The method of claim 11 , wherein an interval between the first and second active fins is less than 40 nm.

14. The method of claim 11 , wherein a part of the third active fin overlaps a part of the fourth active fin in the second direction.

15. The method of claim 11 , further comprising:

forming trenches on both sides of the first to sixth active fins; and

filling the trenches to form an element isolation film, wherein the first to sixth active fins protrude above an upper surface of the element isolation film.

16. A method of fabricating a semiconductor device, the method comprising:

forming a hard mask layer on a substrate;

forming a first sacrificial layer on the hard mask layer opposite the substrate;

forming an upper mandrel that includes at least a first upper sub-mandrel and a second upper sub-mandrel on the first sacrificial layer, the first and second upper sub-mandrels each extending in a first direction and being spaced apart from each other in a second direction that intersects the first direction;

forming first spacers on side walls of the first upper sub-mandrel and the second upper sub-mandrel;

selectively removing the upper mandrel;

etching the first sacrificial layer using the first spacers as etching masks to form a lower mandrel that includes at least first to fourth lower sub-mandrels;

forming second spacers on side walls of the first through fourth lower sub-mandrels;

removing the lower mandrel;

patterning the hard mask layer and the substrate using the second spacers as etching masks to form a fin type pattern, the fin type pattern including first to eighth fins which extend alongside each other in the first direction and are spaced apart from each other in the second direction;

removing the third and sixth fins; and

forming a first gate electrode and a second gate electrode, the first gate electrode extending in the second direction to intersect the first, second, fourth and fifth fins, and the second gate electrode extending in the second direction to intersect the fourth, fifth, seventh and eighth fins while not intersecting the first and second fins, and being spaced apart from the first gate electrode in the first direction.

17. The method of claim 16 , wherein a first interval between the first and second fins is the same as a second interval between the seventh and eighth fins, and wherein a third interval between the second and fourth fins is different from the first interval and is not an integer multiple of the first interval.

18. The method of claim 16 , wherein an interval between the first and second fins is less than 40 nm.

19. The method of claim 16 , wherein the first and second fins intersect the first gate electrode to define a first transistor,

wherein the fourth fin intersects the first gate electrode to define a second transistor, and

wherein the fifth fin intersects the second gate electrode to define a third transistor.

20. The method of claim 16 , wherein the conductivity type of the first transistor is different than the conductivity types of the second and third transistors.

21. A semiconductor device comprising:

first to sixth active fins that extend alongside one another in a first direction;

a first gate electrode that extends in a second direction that intersects the first direction, the first gate electrode intersecting the first to fourth active fins; and

a second gate electrode that extends in the second direction to intersect the third through sixth active fins, the second gate electrode not intersecting the first and second active fins, the second gate electrode spaced apart from the first gate electrode in the first direction,

wherein a first interval between the first and second active fins is the same as a second interval between the fifth and sixth active fins, and wherein a third interval between the second and third active fins is different from the first interval and is not an integer multiple of the first interval,

wherein lengths of the first and second active fins are different from lengths of the third and fourth active fins.