FinFET and method of manufacturing the same

1. A method of manufacturing a Fin Field Effect Transistor (FinFET), comprising:

forming a fin on a semiconductor substrate and an isolation layer surrounding the bottom of the fin;

forming a dummy device including a dummy gate on the fin;

forming an interlayer dielectric layer to cover regions except for the dummy gate;

removing the dummy gate to form an opening;

implanting ions from above the interlayer dielectric layer with the opening therein to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and

forming a replacement gate in the opening.

2. The method according to claim 1 , wherein the ions are implanted at a vertical angle.

3. The method according to claim 2 , wherein the ions are implanted at a dosage in a range of 1E12 cm −2 to 1E14 cm −2 and energy in a range of 10 KeV to 150 KeV.

4. The method according to claim 1 , wherein a first type of dummy device and a second type of dummy device are formed on respective fins.

5. The method according to claim 4 , wherein a first replacement gate and a second replacement gate are formed in respective openings.

6. A Fin Field Effect Transistor (FinFET), comprising:

a semiconductor substrate;

a fin formed on the substrate;

an isolation layer surrounding the bottom of the fin;

a device structure including a gate on the fin and source/drain regions on opposite ends of the fin, with a channel region defined in the fin under the gate between the source/drain regions;

a Punch-Through-Stop Layers (PTSL) in a portion of the fin directly under the gate and beneath the channel region; and

reflection doped layers in portions of the fin on inner sides of source/drain regions and on opposite ends of the channel region, which ends face a respective one of the source/drain regions, and thus disposed between one of the source/drain regions and a corresponding one of the ends of the channel region and between the other of the source/drain regions and a corresponding one of the ends of the channel region, respectively, wherein the reflection doped layers have the same doping type as that of the PTSL.

7. The FinFET according to claim 6 , wherein the device structure comprises a first type of device structure and a second type of device structure.

8. The FinFET according to claim 6 , wherein the reflected doped layers extend along substantially an entire width of the channel region.