IP Library Granted Patent US 9,679,997
Granted Patent B2
US 9,679,997 · App. 15/157,987 · Granted Jun 13, 2017

Semiconductor device with suppressed two-step on phenomenon

Inventor: Akitaka Soeno (Toyota, JP)
Assignee: Toyota Jidosha Kabushiki Kaisha
H01L29/7397H01L29/0696H01L29/0834H01L29/1095H01L29/7395H01L29/36H01L29/861H01L2924/13055
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Quick Facts
Patent No.
US 9,679,997
App. No.
15/157,987
Granted
Jun 13, 2017
Kind
B2
Abstract

A semiconductor device includes an IGBT region with a bottom-body region on a front surface side of an IGBT drift region, an IGBT barrier region on a front surface side of the bottom-body region, and a top-body region on a front surface side of the IGBT barrier region. A diode region is include with a bottom-anode region on a front surface side of the diode drift region, a diode barrier region on a front surface side of the bottom-anode region, a top-anode region on a front surface side of the diode barrier region, and a pillar region extending from the front surface of the semiconductor substrate, piercing the top-anode region, and reaching the diode barrier region, and connected to the front surface electrode and the diode barrier region. An impurity concentration of the top-body region is lower than an impurity concentration of the bottom-anode region.

Claims (23)

1. A semiconductor device comprising:

a semiconductor substrate; and

a front surface electrode configured of metal provided on a front surface of the semiconductor substrate,

wherein

the semiconductor substrate comprises an IGBT (Insulated Gate Bipolar Transistor) region and a diode region,

the IGBT region comprises:

an n-type IGBT drift region;

a p-type bottom-body region provided on a front surface side of the IGBT drift region;

an n-type IGBT barrier region provided on a front surface side of the bottom-body region;

a p-type top-body region provided on a front surface side of the IGBT barrier region;

an n-type emitter region provided on a front surface side of the top-body region; and

a gate trench extending from the front surface of the semiconductor substrate, piercing the emitter region, the top-body region, the IGBT barrier region and the bottom-body region, and reaching the IGBT drift region, and

the diode region comprises:

an n-type diode drift region;

a p-type bottom-anode region provided on a front surface side of the diode drift region;

an n-type diode barrier region provided on a front surface side of the bottom-anode region;

a p-type top-anode region provided on a front surface side of the diode barrier region;

an n-type pillar region extending from the front surface of the semiconductor substrate, piercing the top-anode region, and reaching the diode barrier region, and connected to the front surface electrode and the diode barrier region; and

a gate trench extending from the front surface of the semiconductor substrate, piercing the top-anode region, the diode barrier region and the bottom-anode region, and reaching the diode drift region,

wherein

an average impurity concentration of the top-body region is lower than an average impurity concentration of the bottom-anode region.

2. The semiconductor device according claim 1 , wherein the front surface electrode is configured of titanium.

3. The semiconductor device according claim 1 , wherein a highest impurity concentration of the top-body region is lower than a lowest impurity concentration of the bottom-anode region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA (AKA TOYOTA MOTOR CORPORATION)
To: DENSO CORPORATION
Reel/Frame 052280/0207 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2016
From: SOENO, AKITAKA
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 039307/0026 →
Priority Claims (1)
JP 2015-112904 · Jun 3, 2015 · national
Continuity (1)
Related Publication 20160359027A1 · Dec 8, 2016