Serializer and data transmitter comprising the same

1. A serializer, comprising:

a data signal alignment unit aligning a plurality of data signals with a predetermined phase interval;

a transition detection unit detecting a transition of a logic level among the aligned data signals to generate a toggle signal at a transition of the logic level; and

a toggle signal conversion unit converting the toggle signal into a serial data signal obtained by serializing the data signals,

wherein the transition detection unit compares logic levels of two data signals, of which the phases are continuous, from among the aligned data signals at a same timing, generates a positive toggle signal or a negative toggle signal based on a comparison result of the logic levels of two data signal,

wherein the toggle signal conversion unit receives the positive toggle signal or the negative toggle signal, and outputs the serial data signal and an inverted serial data signal corresponding to an inverted version of the serial data signal.

2. The serializer of claim 1 , wherein the data signal alignment unit aligns the plurality of data signals so as to be spaced apart from each other by a phase difference which corresponds to a value obtained by dividing 360 degrees by the number of the data signals.

3. The serializer of claim 1 , wherein the data signal alignment unit aligns the plurality of data signals so as to have the phase interval while converting the plurality of data signals in a return to zero (RZ) manner.

4. The serializer of claim 3 , wherein the transition detection unit generates the positive toggle signal when a logic level of a data signal of which a phase leads is “0” and a logic level of a data signal of which a phase lags is “1”, and generates the negative toggle signal when a logic level of a data signal of which the phase leads is “1” and a logic level of a data signal of which the phase lags is “0”.

5. The serializer of claim 4 , wherein the toggle signal conversion unit comprises:

a NOR gate SR latch receiving the positive toggle signal and the negative toggle signal and outputting the serial data signal and the inverted serial data signal corresponding to the inverted version of the serial data signal.

6. The serializer of claim 1 , wherein the data signal alignment unit aligns the plurality of data signals so as to have the phase interval while converting the plurality of data signals in a return to one (RO) manner.

7. The serializer of claim 6 , wherein the transition detection unit generates the positive toggle signal when a logic level of a data signal of which a phase leads is “1” and a logic level of a data signal of which a phase lags is “0”, and generates the negative toggle signal when a logic level of a data signal of which a phase leads is “0” and a logic level of a data signal of which a phase lags is “1”.

8. The serializer of claim 7 , wherein the toggle signal conversion unit comprises:

a NAND gate SR latch receiving the positive toggle signal and the negative toggle signal and outputting the serial data signal and an inverted serial data signal corresponding to an inverted version of the serial data signal.

9. The serializer of claim 1 ,

further comprising: a pre-emphasis unit receiving the toggle signal, generating an emphasis signal in an input section of the toggle signal, and making the emphasis signal overlapped with an output signal.

10. A serializer, comprising:

a data signal alignment unit aligning a plurality of data signals with a predetermined phase interval;

a transition detection unit detecting a transition of a logic level among the aligned data signals to generate a toggle signal at a transition of the logic level; and

a toggle signal conversion unit converting the toggle signal into a serial data signal obtained by serializing the data signals,

wherein the data signal alignment unit aligns the plurality of data signals so as to have the phase difference while converting the plurality of data signals in a return to zero (RZ) manner,

wherein the data signal alignment unit comprises a plurality of flip-flops, each of which receives a data signal, a clock signal, and a reset signal and outputs an RZ data signal, obtained by converting the data signal in the RZ manner, and an inverted RZ data signal, corresponding to an inverted version of the RZ data signal, in response to a timing of the clock signal and the reset signal,

wherein a phase difference corresponding to the phase interval exists among the clock signals respectively applied to the flip-flops, and

wherein a phase difference corresponding to the phase interval exists among the reset signals respectively applied to the flip-flops.

11. The serializer of claim 10 , wherein the transition detection unit comprises:

a plurality of first NAND gates, each of which receives two data signals, of which phases are continuous, from among the aligned data signals and performs a NAND operation with respect to an RZ data signal of a data signal, of which a phase leads, and an inverted RZ data signal of a data signal of which a phase lags;

a plurality of second NAND gates, each of which receives two data signals, of which phases are continuous, from among the aligned data signals and performs a NAND operation with respect to an inverted RZ data signal of a data signal, of which a phase leads, and an RZ data signal of a data signal of which a phase lags;

a third NAND gate performing a NAND operation with respect to output signals of the first NAND gates; and

a fourth NAND gate performing a NAND operation with respect to output signals of the second NAND gates.

12. A serializer, comprising:

a data signal alignment unit aligning a plurality of data signals with a predetermined phase interval;

a transition detection unit detecting a transition of a logic level among the aligned data signals to generate a toggle signal at a transition of the logic level; and

a toggle signal conversion unit converting the toggle signal into a serial data signal obtained by serializing the data signals,

wherein the data signal alignment unit aligns the plurality of data signals so as to have the phase interval while converting the plurality of data signals in a return to one (RO) manner,

wherein the data signal alignment unit comprises:

a plurality of flip-flops, each of which receives a data signal, a clock signal, and a reset signal and outputs an RO data signal, obtained by converting the data signal in the RO manner, and an inverted RO data signal, corresponding to an inverted version of the RO data signal, in response to a timing of the clock signal and the reset signal,

wherein a phase difference corresponding to the phase interval exists among the clock signals respectively applied to the flip-flops, and

wherein a phase difference corresponding to the phase interval exists among the reset signals respectively applied to the flip-flops.

13. The serializer of claim 12 , wherein the transition detection unit comprises:

a plurality of first NOR gates, each of which receives two data signals, of which phases are continuous, from among the aligned data signals and performs a NOR operation with respect to an RO data signal of a data signal, of which a phase leads, and an inverted RO data signal of a data signal of which a phase lags;

a plurality of second NOR gates, each of which receives two data signals, of which the phases are continuous, from among the aligned data signals and performs a NOR operation with respect to an inverted RO data signal of a data signal, of which a phase leads, and an RO data signal of a data signal of which a phase lags;

a third NOR gate which performs a NOR operation with respect to output signals of the first NOR gates; and

a fourth NOR gate which performs a NOR operation with respect to output signals of the second NOR gates.