Method and apparatus for system control of a central processing unit (CPU) maximum power detector
A method and apparatus for system control of a central processing unit (CPU) maximum power detector are provided. In accordance with at least one embodiment, a decision is made as to whether a response of a maximum power detector of the CPU is to be altered. When the response is to be altered, a modified input level is provided to the maximum power detector to alter the response. As an example, the modified input level can prevent the maximum power detector from triggering a power throttling function. When the response is not to be altered, an existing input level for the maximum power detector is maintained. In accordance with at least one embodiment, an apparatus or information handling system can comprise a voltage regulator (VR), a current sensor, a CPU comprising a maximum power detector, and a digital to analog converter (DAC).
1. An apparatus comprising:
a power supply unit to generate electrical power;
a voltage regulator (VR) connected to the power supply unit to receive the electrical power;
a current sensor coupled to the VR to sense a current;
a central processing unit (CPU) comprising a maximum power detector, the CPU connected to the current sensor; and
a digital to analog converter (DAC) having a first connection to the power supply unit and a second connection to the current sensor, the DAC producing an output on the second connection to the current sensor that dynamically prevents an operation of the maximum power detector in the CPU based on the current.
2. The apparatus of claim 1 further comprising:
a third connection between a baseboard management controller (BMC) and the DAC, the BMC configured to control the DAC that generates the output.
3. The apparatus of claim 2 wherein the BMC is configured to control the DAC to override a function of the maximum power detector based on the output on the second connection.
4. The apparatus of claim 3 wherein the BMC is configured to control the DAC to override a power throttle trigger function of the maximum power detector based on the output on the second connection.
5. The apparatus of claim 1 wherein the current sensor comprises a sense resistor.
6. The apparatus of claim 1 wherein the current sensor comprises a resistor having a first end coupled to the CPU and a second end coupled to the DAC via the second connection.
7. The apparatus of claim 1 wherein the maximum power detector adds the output produced by the DAC on the second connection.
8. An information handling system comprising:
a power supply unit generating electrical power;
a voltage regulator (VR) connected to the power supply unit to receive the electrical power;
a current sensor coupled to the VR to sense a current;
a central processing unit (CPU) comprising a maximum power detector, the CPU coupled to the current sensor; and
a digital to analog converter (DAC) having a first connection to the power supply unit and a second connection to the current sensor, the DAC producing an output on the second connection to the current sensor that dynamically prevents an operation of the maximum power detector based on the current.
9. The information handling system of claim 8 further comprising:
a third connection between a baseboard management controller (BMC) and the DAC, the BMC configured to control the DAC that generates the output.
10. The information handling system of claim 9 wherein the BMC is configured to control the DAC to override a function of the maximum power detector based on the output on the second connection.
11. The information handling system of claim 10 wherein the BMC is configured to control the DAC to override a power throttle trigger function of the maximum power detector based on the output on the second connection.
12. The information handling system of claim 8 wherein the current sensor comprises a resistor.
13. The information handling system of claim 8 wherein the current sensor comprises a resistor having a first end coupled to the CPU and a second end coupled to the DAC via the second connection.
14. The information handling system of claim 8 wherein the maximum power detector adds the output produced by the DAC on the second connection.
15. A method comprising:
determining if a response of a maximum power detector of a central processing unit (CPU) is to be altered based on a current associated with a current sensor;
when the response of the maximum power detector is to be altered, applying an output generated by an analog to digital converter to the maximum power detector to alter the response, wherein the output generated by the analog to digital converter usurps control over the maximum power detector with respect to triggering a power throttling function of the CPU; and
when the response of the maximum power detector is not to be altered, maintaining an existing voltage for the maximum power detector.
16. The method of claim 15 further comprising:
determining if the output generated by the analog to digital converter has a value that disables the power throttling function;
when the output generated by the analog to digital converter fails to disable the power throttling function, operating the maximum power detector to prevent triggering a power throttling function.
17. The method of claim 16 further comprising:
running a system based on a determined power configuration, wherein the determined power configuration is a result of the determining if the response of the maximum power detector of the CPU is to be altered and the determining if the output generated by the analog to digital converter disables the power throttling function.
18. The method of claim 15 further comprising:
measuring power usage consumed by the central processing unit; and
comparing power usage to a capability of a power supply unit (PSU).
19. The method of claim 18 further comprising obtaining information representative of the capability of the PSU.
20. The method of claim 15 further comprising controlling a trigger that determines the power throttling function.