Double-face display panel
The double-face display panel comprises a plurality of pixel units arranged in an array mode, and the pixel unit comprises an anode, a cathode, an organic material functional layer arranged between the anode and the cathode and at least one thin film transistor, wherein the anode comprises a transmission anode and a reflection anode, the cathode comprises a transmission cathode and a reflection cathode, the transmission anode at least corresponds to the reflection cathode, the transmission cathode at least corresponds to the reflection anode, and the reflection anode and the reflection cathode are arranged in a staggered mode; the transmission anode is electrically connected with a drain electrode of the thin film transistor, and the reflection anode is electrically connected with the drain electrode of the thin film transistor.
1. A double-face display panel, comprising a plurality of pixel units arranged in an array mode, wherein each pixel unit comprises an anode, a cathode, an organic material functional layer arranged between the anode and the cathode and one thin film transistor;
wherein the anode comprises a transmission anode and a reflection anode, the cathode comprises a transmission cathode and a reflection cathode, the transmission anode at least corresponds to the reflection cathode, the transmission cathode at least corresponds to the reflection anode, and the reflection anode and the reflection cathode are arranged in a staggered mode;
the transmission anode is in direct physical contact with the reflection anode, and one of the transmission anode and the reflection anode are in direct physical contact with the drain electrode of the one thin film transistor.
2. The double-face display panel according to claim 1 , wherein the number of the thin film transistors is two, the two thin film transistors are a first thin film transistor and a second thin film transistor;
the drain electrode of the first thin film transistor is electrically connected with the transmission anode, and the drain electrode of the second thin film transistor is electrically connected with the reflection anode;
the double-face display panel further comprises data lines, wherein the data lines comprise a first data line and a second data line;
a source electrode of the first thin film transistor is electrically connected with the first data line, and a source electrode of the second thin film transistor is electrically connected with the second data line.
3. The double-face display panel according to claim 2 , wherein gate electrodes of the first thin film transistor and the second thin film transistor are electrically connected with one gate line simultaneously.
4. The double-face display panel according to claim 1 , wherein both the reflection anode and the reflection cathode comprise a first transparent conductive pattern, a second transparent conductive pattern and a metal conductive pattern between the first transparent conductive pattern and the second transparent conductive pattern.
5. The double-face display panel according to claim 1 , wherein the organic material functional layer at least comprises a hole transport layer, a light emitting layer and an electron transport layer.
6. The double-face display panel according to claim 1 , wherein the double-face display panel further comprises a filling layer arranged between the thin film transistor and an adjacent anode or cathode.
7. The double-face display panel according to claim 1 , further comprising a pixel isolation layer arranged between any two adjacent pixel units, the pixel isolation layer being configured to isolate adjacent pixel units.
8. The double-face display panel according to claim 1 , further comprising a packaging layer for packaging and fixing the double-face display panel.
9. The double-face display panel according to claim 5 , wherein the organic material functional layer further comprises an electron injection layer arranged between the cathode and the electron transport layer, and a hole injection layer arranged between the anode and the hole transport layer.
10. The double-face display panel according to claim 1 , wherein the transmission anode and the reflection anode are arranged at a same layer.
11. The double-face display panel according to claim 1 , wherein the transmission anode and the reflection anode are arranged into upper and lower layers.
12. The double-face display panel according to claim 1 , wherein the anode is arranged close to the thin film transistor.
13. The double-face display panel according to claim 1 , wherein the transmission anode is a portion corresponding to the reflection cathode, and the transmission cathode is a portion corresponding to the reflection anode.
14. The double-face display panel according to claim 1 , wherein the transmission anode comprises a portion corresponding to the reflection cathode and a portion situated below the reflection anode, the transmission cathode comprises a portion corresponding to the reflection anode and a portion situated below the reflection cathode, and the reflection anode and the reflection cathode are arranged in a staggered mode.
15. The double-face display panel according to claim 2 , wherein both the reflection anode and the reflection cathode comprise a first transparent conductive pattern, a second transparent conductive pattern and a metal conductive pattern between the first transparent conductive pattern and the second transparent conductive pattern.
16. The double-face display panel according to claim 3 , wherein both the reflection anode and the reflection cathode comprise a first transparent conductive pattern, a second transparent conductive pattern and a metal conductive pattern between the first transparent conductive pattern and the second transparent conductive pattern.
17. The double-face display panel according to claim 2 , wherein the organic material functional layer at least comprises a hole transport layer, a light emitting layer and an electron transport layer.
18. A double-face display panel, comprising a plurality of pixel units arranged in an array mode and a pixel isolation layer arranged between any two adjacent pixel units, wherein
each pixel unit comprises an anode, a cathode, an organic material functional layer arranged between the anode and the cathode and one thin film transistor,
the anode comprises a transmission anode and a reflection anode, the cathode comprises a transmission cathode and a reflection cathode, the transmission anode at least corresponds to the reflection cathode, the transmission cathode at least corresponds to the reflection anode, and the reflection anode and the reflection cathode are arranged in a staggered mode,
the transmission anode is in direct physical contact with the reflection anode, and one of the transmission anode and the reflection anode are in direct physical contact with the drain electrode of the one thin film transistor,
the pixel isolation layer is configured to isolate adjacent pixel units.