IP Library › Granted Patent US 9,696,771
Granted Patent B2
US 9,696,771 · App. 14/100,483 · Granted Jul 4, 2017

Methods and systems for operating multi-core processors

Inventors: Kang Nam Park (Ansan-si, KR); Eui Youl Ryu (Yongin-si, KR); Young Lak Kim (Seongnam-si, KR); Woo Sung Lee (Seoul, KR); Jae Cheol Lee (Suwon-si, KR); Seung Kon Hwang (Anyang-si, KR)
Assignee: Samsung Electronics Co., Ltd.
G06F1/206G06F1/324G06F1/3206G06F1/329G06F1/3287G06F9/5094Y02B60/1217Y02B60/1275Y02B60/1282Y02B60/142Y02B60/144
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Quick Facts
Patent No.
US 9,696,771
App. No.
14/100,483
Granted
Jul 4, 2017
Kind
B2
Abstract

A method of operating a system on chip (SoC) includes determining to switch from a selected low-power core among a plurality of low-power cores to a high-performance core among a plurality of high-performance cores, counting the number of high-performance cores that are operating among a plurality of high-performance cores, determining a maximum operating frequency of the plurality of high-performance cores based on the counted number, and switching from the selected low-power core to the selected high-performance core based on the determined maximum operating frequency.

Claims (26)

1. A method comprising:

determining to switch from a selected low-power core among a plurality of low-power cores to a high-performance core among a plurality of high-performance cores;

counting a number of high-performance cores that are operating among the plurality of high-performance cores;

determining a maximum operating frequency of the plurality of high-performance cores based on the counted number; and

switching from the selected low-power core to a selected high-performance core of the plurality of high-performance cores based on the determined maximum operating frequency, wherein the switching from the selected low-power core to the selected high-performance core comprises:

storing context of the selected low-power core in a memory;

powering on the selected high-performance core;

powering on an L2 cache of the selected high-performance core;

loading the context of the selected low-power core from the memory to the selected high-performance core; and

powering off the selected low-power core.

2. The method of claim 1 , wherein the determining to switch from the selected low-power core to the selected high-performance core comprises:

measuring a central processing unit (CPU) load of the selected low-power core; and

determining to switch from the selected low-power core to the selected high-performance core when the CPU load exceeds a threshold value.

3. The method of claim 1 , further comprising:

assigning a task to the selected low-power core;

measuring a central processing unit (CPU) load of the selected low-power core assigned with the task; and

adjusting an operating frequency of the selected low-power core based on the CPU load of the selected low-power core.

4. The method of claim 1 , further comprising:

measuring a central processing unit (CPU) load of the selected high-performance core; and

switching from the selected high-performance core to a low-power core when the CPU load of the selected high-performance core is equal to or less than a threshold value.

5. The method of claim 1 , wherein the determining the maximum operating frequency comprises setting the maximum operating frequency of the selected high-performance core to a maximum value among a plurality of predetermined maximum operating frequencies when the counted number is zero.

6. The method of claim 1 , wherein the determined maximum operating frequency of the plurality of high-performance cores is in inverse proportion to the counted number.

7. The method of claim 1 , further comprising;

measuring a temperature of each of the plurality of high-performance cores; and

switching from the selected high-performance core to the selected low-power core based on the temperature.

8. A non-transitory computer readable recording medium for comprising an executable program which, when executed by a processor, performs the method of claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2013
From: PARK, KANG NAM; RYU, EUI YOUL; KIM, YOUNG LAK; LEE, WOO SUNG; LEE, JAE CHEOL; HWANG, SEUNG KON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 031741/0195 →
Priority Claims (1)
KR 10-2012-0147705 · Dec 17, 2012 · national
Continuity (1)
Related Publication 20140173311A1 · Jun 19, 2014