IP Library › Granted Patent US 9,696,912
Granted Patent B2
US 9,696,912 · App. 15/182,861 · Granted Jul 4, 2017

Synchronous input/output command with partial completion

Inventors: David F. Craddock (New Paltz, NY); Mark S. Farrell (Pleasant Valley, NY); Beth A. Glendening (Poughkeepsie, NY); Dale F. Riedy (Poughkeepsie, NY); Peter G. Sutton (Lagrangeville, NY); Harry M. Yudenfriend (Poughkeepsie, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F3/061G06F3/068G06F3/0659G06F13/4243
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Quick Facts
Patent No.
US 9,696,912
App. No.
15/182,861
Granted
Jul 4, 2017
Kind
B2
Abstract

Aspects include communicating synchronous input/output (I/O) commands between an operating system and recipient by issuing a first synchronous I/O command with an initiation bit set, identifying that a mailbox command has been initiated to return control to an operating system before waiting for operations of the first synchronous I/O command to complete, and issuing a second synchronous I/O command with a completion bit set in response to the control returning to the operating system.

Claims (13)

1. A method for synchronous execution of input/output (I/O) commands between an operating system and a recipient, the operating system and the recipient executing on a processor coupled to a memory, the method comprising:

issuing, by the operating system to the recipient, a synchronous I/O initiated command with an initiation bit set;

receiving, from the recipient, a synchronous I/O initiated response identifying that a mailbox command has been initiated to return control to the operating system before waiting for operations of the synchronous I/O initiated command to complete

releasing a processing thread corresponding to the synchronous I/O initiated command in response to the receiving of the synchronous I/O initiated response to permit the synchronous execution of the I/O commands before waiting for the operations of the synchronous I/O initiated command to complete; and

issuing, by the operating system to the recipient, a second synchronous I/O command with a completion bit set in response to the control returning to the operating system.

2. The method of claim 1 , wherein the recipient sends the mailbox command to a persistent storage control unit in response to the synchronous I/O initiated command.

3. The method of claim 1 , wherein the recipient is firmware of the processor.

4. The method of claim 1 , further comprising:

receiving, by the operating system from the recipient, a synchronous I/O complete command response in response to the second synchronous I/O command.

5. The method of claim 4 , wherein the synchronous I/O complete command identifies that a data transfer corresponding to the mailbox command is complete.

6. The method of claim 1 , wherein the synchronous I/O initiated command is issued by a first logical partition of the operating system.

7. The method of claim 6 , further comprising:

issuing, by an operating system of a second logical partition to the recipient, a third synchronous I/O command with an initiation bit set.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2016
From: CRADDOCK, DAVID F.; FARRELL, MARK S.; GLENDENING, BETH A.; RIEDY, DALE F.; SUTTON, PETER G.; YUDENFRIEND, HARRY M.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038921/0854 →
Continuity (2)
Continuation 14872944 · Oct 1, 2015
Related Publication 20170097768A1 · Apr 6, 2017