Complementary RRAM applications for logic and ternary content addressable memory (TCAM)
A ternary content addressable memory (TCAM) cell may include a first resistive memory element, a second resistive memory element, a third resistive memory element, and a first switching element. The first resistive memory element may be disposed between a true data bit line node and a common node. The second resistive memory element may be disposed between a complement data bit line node and the common node. The third resistive element may be coupled to the common node and a word line node. The first switching element may have a control terminal coupled to the common node.
1. A ternary content addressable memory (TCAM) cell comprising:
a first resistive memory element, having a first pair of terminals which are coupled to a true data bit line node and a common node, respectively;
a second resistive memory element having a second pair of terminals which are coupled to a complement data bit line node and the common node, respectively;
a third resistive element having a third pair of terminals which are coupled to the common node and a word line node, respectively; and
a first switching element comprising a control terminal coupled to the common node.
2. The TCAM cell according to claim 1 wherein the first switching element comprises a transistor.
3. The TCAM cell according to claim 1 wherein the first switching element comprises a FET transistor, and the control terminal comprises a gate terminal of the FET transistor.
4. The TCAM cell according to claim 1 wherein the first switching element further comprises first and second non-control terminals; and
one of the first and second non-control terminals is arranged to provide a match node to sense a match voltage during a match operation.
5. The TCAM cell according to claim 1 wherein:
the first switching element further comprises first and second non-control terminals; and
one of the first and second non-control terminals is arranged to provide a read node to sense a read voltage during a verify operation.
6. A ternary content addressable memory (TCAM) array comprising:
a row of at least two TCAM memory cells, wherein a first TCAM memory cell of the at least two TCAM memory cells comprises:
a first resistive memory element, having a first pair of terminals which are coupled to a true data bit line node and a common node, respectively;
a second resistive memory element having a second pair of terminals which are coupled to a complement data bit line node and the common node, respectively;
a third resistive element having a third pair of terminals which are coupled to the common node and a word line node, respectively; and
a first switching element comprising a control terminal coupled to the common node;
wherein:
the word line node is coupled to a common word line;
the first switching element has a first non-control terminal implementing a match node for the first TCAM memory cell; and
the match node of the first TCAM memory cell is coupled to a first row match line.
7. The TCAM array according to claim 6 wherein the true data bit line node is coupled to a corresponding true data bit line of the array and the complement data bit line node is coupled to a corresponding complement data bit line of the array.
8. The TCAM array according to claim 7 and further comprising:
a second row of TCAM memory cells, wherein
a true data bit line node of a second TCAM memory cell of the second row is coupled to a true data bit lines of the array;
a complement data bit line node of the second TCAM memory cell of the second row is coupled to a complement data bit line of the array; and
a match node of the second TCAM memory cell is coupled to a second row match line.
9. The TCAM array according to claim 7 and further comprising:
a conductive path serially connecting the first switching element to a second switching element of a second TCAM memory cell of the row so as to form a serial match string;
wherein the at least two TCAM memory cells are arranged so that the first switching element is turned ON in the case of a match, and turned OFF in the case of a mismatch and the second switching element is turned ON in the case of a match, and turned OFF in the case of a mismatch; and
wherein current flows in the serial match string in the case of a match for the first switching element and the second switching element.
10. The TCAM array according to claim 9 wherein the first switching element comprises a FET transistor, and the control terminal comprises a gate terminal of the FET transistor.
11. The TCAM array according to claim 9 wherein the first TCAM memory cell is programmable to a “don't care” state by programming the third resistive element to a low resistance (Lo-R) state and programming the first resistive memory element and the second resistive memory element to a high resistance (Hi-R) state.
12. The TCAM array according to claim 9 further comprising a conductive path to connect the first switching element to a second switching element of a second TCAM memory cell to apply a serial match string for verify operations.