Semiconductor switching device separated by device isolation
A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
1. A device comprising:
a gate structure formed over a semiconductor substrate, the gate structure having extensions;
a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure; and
source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure, and
wherein the thickness of the extensions is such that electric current flowing through the source/drain regions is prevented from flowing into a photo-sensitive device on an opposite side of the extensions from the source/drain regions.
2. The device of claim 1 , further comprising a sidewall spacer formed on the walls of the gate structure including the gate extensions.
3. The device of claim 1 , wherein the extensions include a first extension and a second extension such that a first end surface of the first extension faces a second end surface of the second extension.
4. The device of claim 3 , wherein a distance from the first end surface to the second end surface is about twice the thickness of a sidewall spacer formed on the walls of the gate structure including the extensions.
5. The device of claim 1 , further comprising a separate dummy gate structure that is positioned adjacent to the extensions.
6. The device of claim 5 , wherein the dummy gate structure is biased.
7. The device of claim 1 , wherein the gate structure and extensions are made of polysilicon.
8. The device of claim 1 , wherein the device isolation structure includes one of: a shallow trench isolation and a doped region.
9. The device of claim 1 , wherein the extensions include a first extension and a second extension, and
wherein a portion of the device isolation structure extends within the semiconductor substrate from the first extension to the second extension such that the gap is bounded by the first and second extensions of the gate structure and the portion of the dielectric isolation structure.
10. A transistor device within an array of photo-sensitive devices, the device comprising:
a device isolation structure formed into a semiconductor substrate;
photo-sensitive devices being isolated by the device isolation structure;
a gate structure formed over the semiconductor substrate, the gate structure having extensions over a portion of the device isolation structure;
a sidewall spacer formed on the sides of the gate structure; and
source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure, and
wherein the thickness of the extensions is such that electric current flowing through the source/drain regions is prevented from flowing into the photo-sensitive devices.
11. The device of claim 10 , wherein the device isolation structure includes a shallow trench isolation structure.
12. The device of claim 10 , wherein the device isolation structure includes a doped region.
13. The device of claim 10 , wherein the extensions include a first extension and a second extension such that a first end surface of the first extension faces a second end surface of the second extension.
14. The device of claim 10 , wherein a distance from the first end surface to the second end surface is about twice the thickness of a sidewall spacer formed on the walls of the gate structure including the extensions.
15. The device of claim 10 , wherein the extensions include a first extension and a second extension, and
wherein a portion of the device isolation structure extends within the semiconductor substrate from the first extension to the second extension such that the gap is bounded by the first and second extensions of the gate structure and the portion of the dielectric isolation structure.
16. The device of claim 10 , wherein the first extension and the second extension include a polysilicon material.
17. A device comprising:
a dielectric isolation feature disposed in a semiconductor substrate;
a photo-sensitive device disposed in the semiconductor substrate adjacent the dielectric isolation feature;
a gate structure disposed over the substrate, wherein the gate structure includes:
a first extension portion extending over the dielectric isolation feature; and
a second extension portion extending over the dielectric isolation feature; and
a source/drain feature disposed in a region of the semiconductor substrate, wherein the region of the substrate is bounded by the first and second extension portions of the gate structure, and
wherein a portion of the dielectric isolation structure extends within the semiconductor substrate from the first extension portion to the second extension portion such that the region of the substrate is bounded by the first and second extension portions of the gate structure and the portion of the dielectric isolation structure.
18. The device of claim 17 , wherein the gate structure includes a main gate structure connecting the first and second extension portions, and
wherein the region of the substrate is bounded by the first and second extension portions, the portion of the dielectric isolation structure, and the main gate structure.
19. The device of claim 17 , wherein the first extension portion has a first end surface and the second extend portion has a second end surface that faces the first end surface, and
wherein the first end surface is spaced apart from the second end surface.
20. The device of claim 17 , further comprising a sidewall spacer disposed along a sidewall of the first extension, wherein the sidewall spacer physically contacts the semiconductor substrate.