IP Library Granted Patent US 9,711,550
Granted Patent B2
US 9,711,550 · App. 14/840,680 · Granted Jul 18, 2017

Pinned photodiode with a low dark current

Inventors: Laurent Favennec (Villard Bonnot, FR); Didier Dutartre (Meylan, FR); Francois Roy (Seyssins, FR)
Assignees: STMicroelectronics SA; STMicroelectronics (Crolles 2) SAS
H01L27/1462H01L27/1461H01L27/1463H01L27/14612H01L27/14685H01L27/14689H01L31/11H01L31/1804Y02E10/547Y02P70/521
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Quick Facts
Patent No.
US 9,711,550
App. No.
14/840,680
Granted
Jul 18, 2017
Kind
B2
Abstract

A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.

Claims (35)

1. A method comprising:

manufacturing a pinned photodiode, the manufacturing including:

forming a conversion region of a first conductivity type on a substrate of a second conductivity type, the conversion region being configured to convert photons into electric charges;

forming a shallow semiconductor region of the second conductivity type on the conversion region;

coating said shallow semiconductor region with a heavily-doped insulator layer that is doped with dopants of the second conductivity type, the shallow semiconductor region being positioned between the conversion region and the heavily-doped insulation layer; and

providing a dopant diffusion from the heavily-doped insulator layer into the shallow semiconductor region, wherein:

the shallow semiconductor region is formed on the conversion region prior to coating said shallow semiconductor region with the heavily-doped insulator layer; and

providing the dopant diffusion includes forming a diffusion layer of the second conductivity type in an upper portion of the shallow semiconductor region, the diffusion layer having a doping level that is higher than a doping level of the shallow semiconductor region.

2. The method of claim 1 , wherein the conversion region is of type N and the layer of a heavily-doped insulator is a boron-doped silicon oxide layer.

3. The method of claim 1 , wherein providing the dopant diffusion includes diffusing dopants from the heavily-doped insulator layer into the shallow semiconductor region to a penetration depth smaller than 50 nm.

4. The method of claim 1 , wherein forming the shallow semiconductor region includes coating the conversion region with the shallow semiconductor region with a maximum doping level in a range from 10 17 to 10 18 at./cm 3 before coating the shallow semiconductor region with the heavily-doped insulator layer.

5. The method of claim 1 , wherein providing the dopant diffusion includes annealing the heavily-doped insulator layer and forming a heavily-doped diffusion layer of the second conductivity type having a doping level that is greater than a doping level of the shallow semiconductor region.

6. The method of claim 2 , wherein the boron-doped silicon oxide layer is doped with a boron concentration from 5×10 21 to 2×10 22 at./cm 3 .

7. The method of claim 3 , wherein the penetration depth is smaller than 10 nm.

8. A pinned photodiode, comprising:

a conversion region of a first conductivity type formed on a substrate of a second conductivity type, the conversion region being configured to convert photons into electric charges;

a diffusion layer of the second conductivity type formed on the conversion region;

a shallow semiconductor region of the second conductivity type positioned between the diffusion layer and the conversion region; and

a heavily-doped insulator layer that coats the diffusion layer, the heavily-doped insulator layer being of the second conductivity type.

9. The pinned photodiode of claim 8 , wherein the heavily-doped insulator layer is boron-doped silicon oxide at a boron concentration from 5×10 21 to 2×10 22 at./cm 3 .

10. The pinned photodiode of claim 8 , wherein the diffusion layer has a depth of less than 50 nm.

11. The pinned photodiode of claim 8 , wherein the shallow semiconductor region has a maximum doping on the order 10 18 at./cm 3 and the diffusion layer has a maximum doping on the order 10 20 at./cm 3 .

12. The pinned photodiode of claim 8 , wherein said diffusion layer has a doping level that is higher than a doping level of the shallow semiconductor region.

13. A device, comprising:

a transfer transistor; and

a pinned photodiode, the pinned photodiode including:

a conversion region of a first conductivity type formed on a substrate of a second conductivity type, the conversion region being configured to convert photons into electric charges;

a diffusion layer of the second conductivity type formed on the conversion region;

a shallow semiconductor region of the second conductivity type positioned between the diffusion layer and the conversion region; and

a heavily-doped insulator layer that coats the diffusion layer, the heavily-doped insulator layer being of the second conductivity type.

14. The device of claim 13 , wherein the heavily-doped insulator layer is boron-doped silicon oxide at a boron concentration from 5×10 21 to 2×10 22 at./cm 3 .

15. The device of claim 13 , wherein the diffusion layer has a depth of less than 10 nm.

16. The device of claim 13 , wherein the transfer transistor includes an insulated gate, a drain, and a source, the source being at least a portion of the conversion region.

17. The device of claim 13 , wherein said diffusion layer has a doping level that is higher than a doping level of the shallow semiconductor region.

18. The device of claim 15 , wherein the shallow semiconductor region has a maximum doping on the order 10 18 at./cm 3 and the diffusion layer has a maximum doping on the order 10 20 at./cm 3 .

Assignments (3)
CHANGE OF NAME Recorded Apr 11, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 067095/0021 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2015
From: FAVENNEC, LAURENT; ROY, FRANCOIS
To: STMICROELECTRONICS (CROLLES 2) SAS
Reel/Frame 036478/0484 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2015
From: DUTARTRE, DIDIER
To: STMICROELECTRONICS SA
Reel/Frame 036478/0500 →
Priority Claims (1)
FR 14 59727 · Oct 10, 2014 · national
Continuity (1)
Related Publication 20160104729A1 · Apr 14, 2016