Apparatuses and methods for controlling data timing in a multi-memory system
Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configure d to delay receipt of the column control signals to the memory.
1. An apparatus comprising:
a plurality of memory units, wherein a memory unit of the plurality of memory units comprises:
a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals;
local control logic configured to provide the row control signals and the column control signals to the memory; and
a configurable delay circuit coupled between the local control logic and the memory, the configurable delay circuit configured to delay receipt of the column control signals at the memory.
2. The apparatus of claim 1 , wherein the configurable delay circuit is configured to delay the column control signals based on timing characteristics of a slowest memory unit of the plurality of memory units.
3. The apparatus of claim 2 , wherein the configurable delay circuit of the slowest memory unit of the plurality of memory units is set to a minimum delay.
4. The apparatus of claim 1 , wherein the configurable delay circuit comprises a plurality of delay gates, wherein a delay is set based on a number of active delay gates of the plurality of delay gates.
5. The apparatus of claim 4 , wherein the memory unit further comprises a fuse bank configured to indicate the number of active delay gates.
6. The apparatus of claim 4 , wherein a master memory unit of the plurality of memory units comprises a control logic configured to provide a signal to the memory unit that indicates the number of active delay gates.
7. The apparatus of claim 4 , wherein the delay makes relative timing of output of associated data from the memory equal to an approximation of relative timing of output of associated data from a memory associated with a slowest memory unit.
8. The apparatus of claim 1 , wherein a master memory unit of the plurality of memory units comprises:
control logic configured to receive memory commands; and
the data pipeline configured to receive associated data from the plurality of memory units.
9. The apparatus of claim 8 , wherein the memory of each of the plurality of memory units is configured to provide an associated control signal, wherein timing of output of the associated control signal is based on timing of output of associated data from the memory, and wherein the data pipeline is further configured to store the data responsive to the associated control signal.
10. The apparatus of claim 9 , wherein the associated control signal from the memory of each of the plurality of memory units is provided to a first in, first out (FIFO) buffer, and wherein the FIFO buffer provides received control signals to the data pipeline.
11. The apparatus of claim 8 , wherein the memory of the master memory unit is configured to provide an associated control signal to the data pipeline, and wherein the data pipeline is further configured to store data received from the memory unit of the plurality of memory units responsive to the associated control signal.
12. The apparatus of claim 1 , wherein each of the plurality of memory units have the same architecture.