IP Library › Granted Patent US 9,716,161
Granted Patent B2
US 9,716,161 · App. 14/503,994 · Granted Jul 25, 2017

Gate structure having designed profile and method for forming the same

Inventors: Kai-Li Cheng (Taipei, TW); Che-Cheng Chang (New Taipei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/66545H01L21/28114H01L21/32135H01L29/42376H01L29/66636H01L29/7848H01L21/28079H01L21/28088H01L29/165H01L29/4958H01L29/4966H01L29/517
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Quick Facts
Patent No.
US 9,716,161
App. No.
14/503,994
Granted
Jul 25, 2017
Kind
B2
Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a metal gate structure having curved sidewalls formed over a substrate. The semiconductor structure further includes spacers formed on the curved sidewalls of the metal gate structure. In addition, each curved sidewall of the metal gate structure has a top portion, a middle portion, and a bottom portion, and an angle between the middle portion and the bottom portion of the curved sidewall of the metal gate structure is smaller than 180° C.

Claims (39)

1. A method for forming a semiconductor structure, comprising:

forming a polysilicon layer over a substrate;

forming a hard mask structure over the polysilicon layer;

etching the polysilicon layer to form a dummy gate structure below the hard mask structure;

forming spacers over sidewalls of the dummy gate structure; and

replacing the dummy gate structure by a metal gate structure,

wherein the dummy gate structure has a top width, a neck width, and a bottom width, and the neck width is larger than both the top width and the bottom width.

2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the step of etching the polysilicon layer to form the dummy gate structure further comprises:

etching the polysilicon layer to form an upper portion of the dummy gate structure by a first etching process; and

etching the polysilicon layer to form a bottom portion of the dummy gate structure by a second etching process,

wherein a first etching gas and a second gas are used in both the first etching process and the second etching process, and a volume ratio of the first etching gas to the second etching gas used in the first etching process is smaller than a volume ratio of the first etching gas to the second etching gas used in the second etching process.

3. The method for forming a semiconductor structure as claimed in claim 2 , wherein the first etching gas is CF 4 , and the second etching gas is Cl 2 .

4. The method for forming a semiconductor structure as claimed in claim 1 , wherein a ratio of the neck width to the top width is in a range from about 1.01 to about 1.51.

5. The method for forming a semiconductor structure as claimed in claim 1 , wherein a ratio of the neck width to the bottom width is in a range from about 1.01 to about 1.44.

6. The method for forming a semiconductor structure as claimed in claim 1 , wherein the top width is a width of a top surface of the dummy gate structure, the bottom width is a width of a bottom surface of the dummy gate structure, and the neck width is the largest width of the dummy gate structure measured from a position located between the top surface and the bottom surface of the dummy gate structure.

7. The method for forming a semiconductor structure as claimed in claim 6 , wherein a first distance is measured from the top surface to the bottom surface of the dummy gate structure, a second distance is measured from the bottom surface of the dummy gate structure to the position from which the neck width is measured, and a ratio of the second distance to the first distance is in a range from about 0.26 to about 0.39.

8. The method for forming a semiconductor structure as claimed in claim 1 , wherein the metal gate structure has a top surface, a bottom surface, and a curved sidewall, and an angle between the top surface and the curved sidewall and an angle between the bottom surface and the curved sidewall are both larger than 90°.

9. A method for forming a semiconductor structure, comprising:

forming a dummy gate layer over a substrate;

patterning a top portion of the dummy gate layer to form an upper portion of a dummy gate structure by performing a first etching process; and

patterning a bottom portion of the dummy gate layer to form a bottom portion of the dummy gate structure by performing a second etching process,

wherein the first etching process is different from the second etching process, such that a first inclination of a sidewall of the upper portion is different from a second inclination of a sidewall of the bottom portion.

10. The method for forming a semiconductor structure as claimed in claim 9 , wherein both the first etching process and the second etching process comprise using a first etching gas and a second etching gas, but a volume ratio of the first etching gas to the second etching gas used in the first etching process is different from a volume ratio of the first etching gas to the second etching gas used in the second etching process.

11. The method for forming a semiconductor structure as claimed in claim 10 , wherein the first etching gas comprises CF 4 , CH 2 F 2 , or CHF 3 , and the second etching gas comprises Cl 2 , HBr, or SF 6 .

12. The method for forming a semiconductor structure as claimed in claim 11 , further comprising:

replacing the dummy gate structure by a metal gate structure,

wherein the metal gate structure has curved sidewalls.

13. The method for forming a semiconductor structure as claimed in claim 10 , wherein the volume ratio of the first etching gas to the second etching gas used in the first etching process is smaller than the volume ratio of the first etching gas to the second etching gas used in the second etching process, such that the first inclination of the sidewall of the upper portion is smaller than the second inclination of the sidewall of the bottom portion.

14. The method for forming a semiconductor structure as claimed in claim 13 , wherein the upper portion of the dummy gate structure has a first height, and the bottom portion of the dummy gate structure has a second height, and a ratio of the first height to the second height is in a range from about 1.5 to about 3.

15. The method for forming a semiconductor structure as claimed in claim 9 , wherein an angle between the first inclination and the second inclination measured from an inner side of the dummy gate structure is smaller than 180°.

16. A method for forming a semiconductor structure, comprising:

forming a dummy gate layer over a substrate;

patterning the dummy gate layer to form a dummy gate structure having an upper portion and a bottom portion such that a first inclination of a sidewall of the upper portion of the dummy gate structure is smaller than a second inclination of a sidewall of the bottom portion of the dummy gate structure; and

replacing the dummy gate structure by a metal gate structure,

wherein an angle between the first inclination and the second inclination measured from an inner side of the dummy gate structure is smaller than 180°.

17. The method for forming a semiconductor structure as claimed in claim 16 , wherein the upper portion of the dummy gate structure is formed by performing a first etching process and the bottom portion of the dummy gate structure is formed by performing a second etching process, the first etching process is different from the second etching process.

18. The method for forming a semiconductor structure as claimed in claim 17 , wherein both the first etching process and the second etching process comprise using a first etching gas and a second etching gas, but a volume ratio of the first etching gas to the second etching gas used in the first etching process is smaller than a volume ratio of the first etching gas to the second etching gas used in the second etching process.

19. The method for forming a semiconductor structure as claimed in claim 16 , wherein the dummy gate structure has a top width at its top surface, a bottom width at its bottom surface, and a neck width at a middle of the dummy gate structure, and the neck width is larger than the top width and the bottom width.

20. The method for forming a semiconductor structure as claimed in claim 16 , wherein the dummy gate layer is a polysilicon layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2014
From: CHENG, KAI-LI; CHANG, CHE-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
Reel/Frame 033946/0628 →
Continuity (1)
Related Publication 20160099337A1 · Apr 7, 2016