Methods for forming crystalline IGZO with a seed layer
Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A seed layer is formed above the substrate. The seed layer has a crystalline structure that is substantially dominant along the c-axis. An IGZO layer is formed above the seed layer. The seed layer may include zinc oxide. A stack of alternating seed layers and IGZO layers may be formed.
1. A method for forming an indium-gallium-zinc oxide (IGZO) device, the method comprising:
providing a substrate;
forming a seed layer above the substrate, wherein the seed layer has a crystalline structure that is substantially dominant along the c-axis;
forming a channel layer above the seed layer, wherein the channel layer comprises a plurality of alternating first sub-layers and second sub-layers, each of the first sub-layers of the channel layer comprises IGZO, and each of the second sub-layers of channel layer has a crystalline structure that is substantially dominant along the c-axis; and
forming a source region and a drain region above the channel layer.
2. The method of claim 1 , wherein one of the first sub-layers of the channel layer is formed adjacent to the seed layer.
3. The method of claim 1 , wherein the seed layer comprises zinc oxide.
4. The method of claim 3 , wherein the seed layer has a thickness of between about 2 nanometers (nm) and about 10 nm.
5. The method of claim 4 , wherein each of the second sub-layers of the channel layer comprises zinc oxide.
6. The method of claim 5 , wherein each of the first sub-layers of the channel layer and each of the second sub-layers of the channel layer has a thickness between about 2 nm and about 10 nm.
7. The method of claim 1 , further comprising forming a gate electrode above the substrate, wherein the seed layer is formed above the gate electrode.
8. The method of claim 7 , further comprising forming a gate dielectric layer above the gate electrode, wherein the seed layer is formed above the gate dielectric layer.
9. A method for forming an indium-gallium-zinc oxide (IGZO) device, the method comprising:
providing a substrate;
forming a seed layer above the substrate, wherein the seed layer comprises zinc oxide;
forming a channel layer above the seed layer, wherein the channel layer consists of a plurality of alternating first sub-layers and second sub-layers, each of the first sub-layers of the channel layer comprises IGZO, each of the second sub-layers of channel layer comprises zinc oxide, and one of the first sub-layers of the channel layer is formed directly on the seed layer; and
forming a source region and a drain region above the channel layer.
10. The method of claim 9 , wherein the seed layer has a thickness of between about 2 nanometers (nm) and about 10 nm.
11. The method of claim 10 , wherein each of the first sub-layers of the channel layer and each of the second sub-layers of the channel layer has a thickness between about 2 nm and about 10 nm.
12. The method of claim 11 , wherein the source region and the drain region are formed directly on one of the first sub-layers of the channel layer.
13. The method of claim 11 , further comprising forming a gate electrode above the substrate, wherein the seed layer is formed above the gate electrode.
14. The method of claim 13 , further comprising forming a gate dielectric layer above the gate electrode, wherein the seed layer is formed above the gate dielectric layer.
15. The method of claim 14 , wherein each of the source region and the drain region comprises titanium, molybdenum, copper, copper-manganese alloy, or a combination thereof.
16. A method for forming an indium-gallium-zinc oxide (IGZO) thin-film transistor, the method comprising:
providing a substrate;
forming a gate electrode above the substrate;
forming a seed layer above the gate electrode, wherein the seed layer comprises zinc oxide;
forming a channel layer above the seed layer, wherein the channel layer comprises a plurality of alternating first sub-layers and second sub-layers, each of the first sub-layers of the channel layer comprises IGZO, and each of the second sub-layers of channel layer has a crystalline structure that is substantially dominant along the c-axis; and
forming a source region and a drain region above the channel layer.
17. The method of claim 16 , wherein the seed layer has a thickness of between about 2 nanometers (nm) and about 10 nm.
18. The method of claim 17 , wherein each of the first sub-layers of the channel layer and each of the second sub-layers of the channel layer has a thickness between about 2 nm and about 10 nm.
19. The method of claim 18 , further comprising forming a gate dielectric layer above the gate electrode, wherein the seed layer is formed above the gate dielectric layer.
20. The method of claim 17 , wherein each of the second sub-layers of the channel layer comprises zinc oxide.