Apparatuses and methods for providing data to a configurable storage area
Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.
1. An apparatus, comprising:
an extended address register including a plurality of configuration bits indicative of an offset and a size;
an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits;
a buffer configured to store data in a plurality of cache lines, each cache line of the plurality of cache lines having a respective usage field, the data including data to be stored in the storage area and further including data not to be stored in the storage area, the data to be stored in the storage area and data not to be stored in the storage area identified by information included in the respective usage field of the cache line of the plurality of cache lines in which the data is stored, each respective usage field of each respective cache line indicating whether the respective cache line is in use and includes write data not yet stored in the storage area; and
a memory control circuit coupled to the buffer and configured to identify data to be stored in the storage area based on information included in the respective usage fields of the plurality of cache lines in which data is stored, and responsive, at least in part, to a flush command, cause the buffer to store the data identified as data to be stored in the storage area in the storage area of the array and to not store the data identified as data not to be stored in the storage area until after the data to be stored in the storage area is stored; wherein the memory control circuit is further configured to interrupt the flush command to prepare for a read command or a write command and resume the flush command once the read command or the write command is performed.
2. The apparatus of claim 1 , wherein the data includes data not to be stored in the storage area, the memory control circuit further configured to cause the buffer to store the data not to be stored in the storage area after causing the buffer to store the data to be stored in the storage area.
3. The apparatus of claim 1 , further comprising:
a flag status register including a flush bit, the flush bit configured to indicate whether the buffer includes data to be stored in the storage area.
4. The apparatus of claim 3 , wherein the memory control circuit is further configured to change the state of the flush bit responsive, at least in part, to the flush command.
5. The apparatus of claim 1 , wherein the array comprises non-volatile memory.
6. The apparatus of claim 1 , wherein the apparatus is included in a memory.
7. An apparatus, comprising:
an array having a storage area, the storage area having a size based on a first plurality of configuration bits and an offset based on a second plurality of configuration bits, wherein the size indicates a size of the storage area relative to a size of the array and the offset indicates an offset of the storage area relative to the size of the array;
a buffer coupled to the array and comprising a plurality of cache lines, each cache line of the plurality of cache lines configured to store data and further configured to store information in a respective usage field to indicate whether the cache line is in use and includes data not yet stored in the storage area of the array; and
a memory control circuit coupled to the buffer and configured to identify data stored in the buffer as data to be stored in the storage area based on the information in the respective usage field of the cache line in which the data is stored in the buffer, and responsive, at least in part, to a flush command, to cause the buffer to provide only data identified based on the information of the respective usage field as data to be stored in the storage area to the array to be stored; wherein the memory control circuit is further configured to interrupt the flush command to prepare for a read command or a write command and resume the flush command once the read command or the write command is performed.
8. The apparatus of claim 7 , wherein the memory control circuit is further configured to cause another cache line of the plurality of cache lines to provide write data to the array responsive, at least in part, to a write command.
9. The apparatus of claim 7 , wherein the memory control circuit is configured to adjust the size by modifying the first plurality of configuration bits and adjust the offset by modifying the second plurality of configuration bits.
10. The apparatus of claim 7 , further comprising:
an extended address register configured to store the configuration bits.
11. The apparatus of claim 7 , wherein the array comprises non-volatile memory.
12. The apparatus of claim 7 , further comprising:
a host coupled to the memory control circuit and configured to provide the flush command.
13. A method, comprising:
storing write data in a cache line of a buffer, the write data including write data associated with a storage area of an array;
determining whether the cache line includes the write data associated with a storage area of the array, wherein the cache line includes a usage field indicating whether the cache line is in use and includes write data not yet stored in the storage area; and
providing only the write data associated with the storage area to the storage area responsive, at least in part, to a flush command,
wherein at least one of a size or offset of the storage area is based, at least in part, on a plurality of configuration bits; wherein the memory control circuit is further configured to interrupt the flush command to prepare for a read command or a write command and resume the flush command once the read command or the write command is performed.
14. The method of claim 13 , wherein the write data includes write data not associated with the storage area, the method further comprising:
after providing the write data associated with the storage area to the storage area, providing the write data not associated with the storage area to the array.
15. The method of claim 13 , further comprising:
after providing the write data associated with the storage area to the storage area, changing the state of a flush bit of a flag status register.
16. The method of claim 13 , further comprising:
providing the state of a flush bit responsive, at least in part, to receipt of a read flag status register command.
17. The method of claim 13 , wherein providing the write data associated with the storage area to the storage area responsive, at least in part, to a flush command comprises:
storing the write data in non-volatile memory.
18. The method of claim 13 , further comprising:
indicating, with a usage field of the cache line, that the cache line includes the write data associated with a storage area of the array.