Peripheral equipment control device and information processing
Disclosed herein is a peripheral equipment control device controlling data flow via a peripheral equipment, the peripheral equipment control device including: a peripheral equipment control processor that can control an operation of one or more peripheral equipment; and a bus adapted to connect the peripheral equipment control processor, a main processor, and the one or more peripheral equipment, the main processor being provided outside the peripheral equipment control device to control the operation of the one or more peripheral equipment, in which the bus stores addresses that are referenced by the main processor and the peripheral equipment control processor to access the one or more peripheral equipment, and the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is active.
1. A peripheral equipment control device controlling data flow via a peripheral equipment, the peripheral equipment control device comprising:
a peripheral equipment control processor that controls an operation of at least one peripheral equipment; and
a bus adapted to connect the peripheral equipment control processor, a main processor, and the peripheral equipment, the main processor being provided outside the peripheral equipment control device to control the operation of the peripheral equipment,
wherein the bus stores addresses that are referenced by the main processor and the peripheral equipment control processor to access the peripheral equipment, and the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is active,
wherein each of the peripheral equipment includes a storage device adapted to store data accessible by the main processor and the peripheral equipment control processor,
wherein data stored in the storage device includes an operating system program executed by the main processor to control the operation of the peripheral equipment control device and the peripheral equipment,
wherein the bus stores a first storage device reference address used to access arbitrary data stored in the storage device and a second storage device reference address used to access the area of the storage device other than that which stores the operating system program of all the data stored in the storage device, and the bus prohibits the peripheral equipment control processor from referencing the first storage device reference address,
wherein the peripheral equipment control device further comprises an access indicator storage section adapted to store an access yes/no indicator that indicates whether or not the peripheral equipment control processor can reference the second storage device reference address,
wherein the bus permits the peripheral equipment control processor to reference the second storage device reference address when the access yes/no indicator stored in the access indicator storage section indicates that the second storage device reference address can be referenced by the peripheral equipment control processor,
wherein the bus prohibits the peripheral equipment control processor from referencing the second storage device reference address when the access yes/no indicator stored in the access indicator storage section indicates that the second storage device reference address is not referenced by the peripheral equipment control processor, and
wherein the access indicator storage section prohibits the peripheral equipment control processor from making a change to the access yes/no indicator.
2. The peripheral equipment control device of claim 1 , wherein the bus permits access to the peripheral equipment by the peripheral equipment control processor while the main processor is inactive.
3. The peripheral equipment control device of claim 1 , wherein the bus stores editing reference addresses that are referenced to change the association between addresses stored in a control address storage section and the peripheral equipment, permits the main processor to reference the editing reference addresses, and prohibits the peripheral equipment control processor from referencing the editing reference addresses.
4. The peripheral equipment control device of claim 1 , further comprising:
a system control section adapted to control the activation of the main processor and the peripheral equipment control processor by controlling the energization of the main processor and the peripheral equipment control processor; and
an energization indicator storage section adapted to store an energization yes/no indicator adapted to indicate whether or not the peripheral equipment control processor can be energized when the main processor is inactive, wherein
the system control section references the energization yes/no indicator stored in the energization indicator storage section if the main processor is inactive and maintains the peripheral equipment control processor energized if the energization yes/no indicator permits the energization of the peripheral equipment control processor.
5. An information processing device comprising:
a peripheral equipment control device adapted to control data flow via a peripheral equipment; and
a main processor provided outside the peripheral equipment control device to control the operation of at least one peripheral equipment, wherein
the peripheral equipment control device includes
a peripheral equipment control processor that controls the operation of the at least one peripheral equipment; and
a bus adapted to connect the peripheral equipment control processor, the main processor, and the peripheral equipment, the bus also adapted to store addresses that are referenced by the main processor and the peripheral equipment control processor to access the at least one peripheral equipment, and
the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is energized and active,
wherein the peripheral equipment includes a storage device adapted to store data accessible by the main processor and the peripheral equipment control processor,
wherein data stored in the storage device includes an operating system program executed by the main processor to control the operation of the peripheral equipment control device and the peripheral equipment,
wherein the bus stores a first storage device reference address used to access arbitrary data stored in the storage device and a second storage device reference address used to access the area of the storage device other than that which stores the operating system program of all the data stored in the storage device, and the bus prohibits the peripheral equipment control processor from referencing the first storage device reference address,
wherein the peripheral equipment control device further comprises an access indicator storage section adapted to store an access yes/no indicator that indicates whether or not the peripheral equipment control processor can reference the second storage device reference address,
wherein the bus permits the peripheral equipment control processor to reference the second storage device reference address when the access yes/no indicator stored in the access indicator storage section indicates that the second storage device reference address can be referenced by the peripheral equipment control processor,
wherein the bus prohibits the peripheral equipment control processor from referencing the second storage device reference address when the access yes/no indicator stored in the access indicator storage section indicates that the second storage device reference address is not referenced by the peripheral equipment control processor, and
wherein the access indicator storage section prohibits the peripheral equipment control processor from making a change to the access yes/no indicator.
6. A peripheral equipment control device controlling data flow via a peripheral equipment, the peripheral equipment control device comprising:
a peripheral equipment control processor that can control an operation of at least one peripheral equipment; and
a bus adapted to connect the peripheral equipment control processor, a main processor, and the peripheral equipment, the main processor being provided outside the peripheral equipment control device to control the operation of the peripheral equipment,
wherein the bus stores addresses that are referenced by the main processor and the peripheral equipment control processor to access the peripheral equipment, and the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is active,
wherein each of the peripheral equipment includes a storage device adapted to store data accessible by the main processor and the peripheral equipment control processor,
wherein data stored in the storage device includes an operating system program executed by the main processor to control the operation of the peripheral equipment control device and the peripheral equipment, and
wherein the bus stores a first storage device reference address used to access arbitrary data stored in the storage device and a second storage device reference address used to access the area of the storage device other than that which stores the operating system program of all the data stored in the storage device, and the bus prohibits the peripheral equipment control processor from referencing the first storage device reference address
the peripheral equipment control device further comprising:
an access indicator storage section adapted to store an access yes/no indicator that indicates whether or not the peripheral equipment control processor can reference the second storage device reference address, wherein
the bus permits the peripheral equipment control processor to reference the second storage device reference address when the access yes/no indicator stored in the access indicator storage section indicates that the second storage device reference address can be referenced by the peripheral equipment control processor, and
the bus prohibits the peripheral equipment control processor from referencing the second storage device reference address when the access yes/no indicator stored in the access indicator storage section indicates that the second storage device reference address is not referenced by the peripheral equipment control processor.