Multi bit capacitorless DRAM and manufacturing method thereof
A multi-bit capacitorless DRAM according to the embodiment of the present invention may be provided that includes: a substrate; a source and a drain formed on the substrate; a plurality of nanowire channels formed on the substrate; a gate insulation layer formed in the plurality of nanowire channels; and a gate formed on the gate insulation layer. Two or more nanowire channels among the plurality of nanowire channels have different threshold voltages. Each of the nanowire channels includes: a silicon layer; a first epitaxial layer which is formed to surround the silicon layer; and a second epitaxial layer which is formed to surround the first epitaxial layer. As a result, the high integration multi-bit capacitorless DRAM which operates at multi-bits can be implemented and a performance of accumulating excess holes can be improved by using energy band gap.
1. A multi-bit capacitorless DRAM comprising:
a substrate;
a source and a drain formed on the substrate;
a plurality of nanowire channels formed on the substrate;
a gate insulation layer formed in the plurality of nanowire channels; and
a gate formed on the gate insulation layer,
wherein two or more nanowire channels among the plurality of nanowire channels have different threshold voltages.
2. The multi-bit capacitorless DRAM of claim 1 , wherein the two or more nanowire channels have different threshold voltages by changing at least one of a kind, depth, concentration, and angle of a doped ion.
3. The multi-bit capacitorless DRAM of claim 1 , wherein the two or more nanowire channels have different threshold voltages by changing a shape or area of the cross-section of each of the nanowire channels.
4. The multi-bit capacitorless DRAM of claim 1 , wherein the two or more nanowire channels have different shapes or areas of the cross-sections thereof by changing at least one of a kind and a concentration of an etching material, an etching time period, a degree of a vacuum, and an etching temperature.
5. The multi-bit capacitorless DRAM of claim 1 , wherein each of the nanowire channels comprises:
a silicon layer;
a first epitaxial layer which is formed to surround the silicon layer; and
a second epitaxial layer which is formed to surround the first epitaxial layer.
6. The multi-bit capacitorless DRAM of claim 5 , wherein the first epitaxial layer is a Si 1-x Ge x layer grown by epitaxy.
7. The multi-bit capacitorless DRAM of claim 5 , wherein the first epitaxial layer is a Si 1-x C x layer grown by epitaxy.
8. The multi-bit capacitorless DRAM of claim 5 , wherein the second epitaxial layer is a silicon layer grown by epitaxy.
9. The multi-bit capacitorless DRAM of claim 1 , wherein each of the nanowire channels comprises:
a first silicon layer; and
a second silicon layer which is formed to surround the first silicon layer.
10. The multi-bit capacitorless DRAM of claim 9 , wherein the first silicon layer is a silicon layer p-type doped from n-type by an ion implantation process.
11. The multi-bit capacitorless DRAM of claim 9 , wherein the second silicon layer is a p-type silicon layer into which an ion is not implanted.
12. The multi-bit capacitorless DRAM of claim 1 , further comprising:
a controller which controls operations of the multi-bit capacitorless DRAM; and
a storage unit which stores a driving voltage for each of the plurality of nanowire channels, wherein the driving voltage is based on threshold voltages of the plurality of nanowire channels,
wherein the controller controls a driving voltage which is applied to at least one of the gate and the drain, and programs or erases two or more bit data.
13. A method for manufacturing a multi-bit capacitorless DRAM, the method comprising:
(a) depositing a hard mask on a substrate;
(b) etching at least a portion of the hard mask;
(c) patterning a nanowire on the substrate by anisotropic etching;
(d) forming a passivation layer on the substrate;
(e) forming a nanowire channel on the substrate by isotropic etching;
(f) forming a plurality of the nanowire channels by repeatedly performing the steps (c) to (e); and
(g) forming a source, a drain and a gate,
wherein the plurality of nanowire channels are processed to have different threshold voltages respectively by the step (f).
14. The method of claim 13 , wherein, in the step (f), every time when each nanowire channel is formed, dopant is implanted with the change of at least one of a kind, depth, concentration, and implantation angle of a doped ion, so that the plurality of nanowire channels have different threshold voltages respectively.
15. The method of claim 13 , wherein, in the step (f), every time when each nanowire channel is formed, at least one of a kind and concentration of an etching material, etching time period, a degree of a vacuum, and an etching temperature is changed, so that the plurality of nanowire channels have different threshold voltages respectively.
16. The method of claim 13 , wherein, in the step (f), a first epitaxial layer and a second epitaxial layer are formed in the plurality of nanowire channels.
17. The method of claim 16 , wherein the first epitaxial layer is a Si 1-x Ge x layer which surrounds the nanowire channel and is grown by epitaxy.
18. The method of claim 16 , wherein the first epitaxial layer is a Si 1-x C x layer which surrounds the nanowire channel and is grown by epitaxy.
19. The method of claim 13 , wherein the second epitaxial layer is a silicon layer which surrounds the first epitaxial layer and is grown by epitaxy.
20. The method of claim 13 , wherein, in the step (f), an n-type silicon layer is formed in each of the plurality of nanowire channels by an ion implantation process.