IP Library Granted Patent US 9,735,310
Granted Patent B2
US 9,735,310 · App. 15/280,247 · Granted Aug 15, 2017

Damage-and-resist-free laser patterning of dielectric films on textured silicon

Inventor: Mark Scott Bailly (Chandler, AZ)
Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
H01L31/1804H01L31/028H01L31/02167H01L31/022441H01L31/0682
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Quick Facts
Patent No.
US 9,735,310
App. No.
15/280,247
Granted
Aug 15, 2017
Kind
B2
Abstract

In accordance with embodiments disclosed herein, there are provided methods and systems for implementing damage-and-resist-free laser patterning of dielectric films on textured silicon. For example, in one embodiment, such means include means for depositing a Silicon nitride (SiNx) or SiOx (silicon oxide) layer onto a crystalline silicon (c-Si) substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) processing; depositing an amorphous silicon (a-Si) film on top of the SiNx or SiOx layer; patterning the a-Si film to define an etch mask for the SiNx or SiOx layer; removing the SiNx or SiOx layer via a Buffered Oxide Etch (BOE) chemical etch to expose the c-Si surface; removing the a-Si mask with a hydrogen plasma etch in a PECVD tool to prevent current loss from the mask; and plating the exposed c-Si surface with metal contacts. Other related embodiments are disclosed.

Claims (44)

1. A method comprising:

depositing a Silicon nitride (SiNx) or SiOx (silicon oxide) layer onto a crystalline silicon (c-Si) substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) processing;

depositing an amorphous silicon (a-Si) film on top of the SiNx or SiOx layer;

patterning the a-Si film to define an etch mask for the SiNx or SiOx layer;

removing the SiNx or SiOx layer via a Buffered Oxide Etch (BOE) chemical etch to expose the c-Si surface;

removing the a-Si mask; and

plating the exposed c-Si surface with metal contacts.

2. The method of claim 1 , wherein removing the a-Si mask comprises removing the a-Si mask with a dilute Potassium Hydroxide (KOH).

3. The method of claim 1 , wherein removing the a-Si mask comprises removing the a-Si mask with a hydrogen plasma etch in a PECVD tool to prevent current loss from the mask.

4. The method of claim 1 :

wherein the a-Si film comprises a sacrificial a-Si layer deposited on top of the SiNx or SiOx layer; and

wherein patterning the a-Si film to define the etch mask for the SiNx or SiOx layer comprises patterning the sacrificial a-Si layer with a laser.

5. The method of claim 4 , wherein removing the a-Si mask removing the a-Si mask via a low power hydrogen plasma etch in a PECVD tool to prevent current loss from the mask, wherein the removal of the a-Si mask exposes the c-Si surface, and wherein the exposed c-Si surface is free from damage from the laser.

6. The method of claim 1 , wherein depositing the amorphous silicon (a-Si) film on top of the SiNx or SiOx layer prepares the film for metallization without damaging the underlying crystalline silicon (c-Si) substrate.

7. The method of claim 1 , wherein the a-Si film is susceptible to laser removal, but is non-reactive to the BOE chemical etch.

8. The method of claim 1 , wherein the layer formed from SiNx or SiOx is sensitive to the BOE chemical etch, but is not sensitive to the laser.

9. The method of claim 1 , wherein plating the exposed c-Si surface with metal contacts comprises plating the exposed c-Si surface with metal contacts having a size less than 20 microns in diameter or width.

10. The method of claim 1 :

wherein patterning the a-Si film to define the etch mask for the SiNx or SiOx layer comprises patterning via a laser; and

wherein plating the exposed c-Si surface with metal contacts comprises depositing the metal contacts via Light-Induced-Plating (LIP) in areas defined by the patterning via the laser.

11. The method of claim 1 :

wherein the method produces a solar cell under manufacture;

wherein patterning the a-Si film to define the etch mask for the SiNx or SiOx layer comprises patterning the SiNx or SiOx layer without patterning any busbar of the solar cell under manufacture; and

wherein press on tin coated copper wires are fabricated onto the solar cell under manufacture in lieu of the busbars.

12. The method of claim 1 , wherein depositing the amorphous silicon (a-Si) film on top of the SiNx or SiOx layer comprises depositing the a-Si film as a sacrificial a-Si layer via a screen printing process and lithographically exposing the sacrificial a-Si layer to light.

13. The method of claim 12 :

wherein lithographically exposing the sacrificial a-Si layer to light comprises patterning the patterning the a-Si film to define the etch mask for the SiNx or SiOx layer via an ultraviolet laser.

14. The method of claim 1 , wherein removing the SiNx or SiOx layer via a Buffered Oxide Etch (BOE) chemical etch to expose the c-Si surface comprises removing the SiNx or SiOx layer via buffered hydrofluoric acid which etches the layer formed from the SiNx or SiOx but is non-reactive with the a-Si mask.

15. The method of claim 1 :

wherein depositing the SiNx or SiOx layer onto the c-Si substrate by the PECVD processing comprises depositing the depositing the SiNx or SiOx layer via a PECVD tool; and

wherein depositing the a-Si film on top of the SiNx or SiOx layer comprises depositing the a-Si film via the PECVD tool used to deposit the depositing the SiNx or SiOx layer during one operation by changing gas flows of the PECVD tool during the one operation.

16. The method of claim 1 , wherein plating the exposed c-Si surface with metal contacts comprises plating a potential photovoltaic cell under manufacture formed from the exposed c-Si surface with metal contacts, the metal contacts forming electrically conductive metallic pathways on a top surface of the potential photovoltaic cell.

17. A method of manufacturing a photovoltaic cell, wherein the method comprises:

forming a substrate of the photovoltaic cell from crystalline silicon (c-Si) to form a c-Si substrate of the photovoltaic cell;

depositing a Silicon nitride (SiNx) or SiOx (silicon oxide) layer onto the c-Si substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) processing;

depositing an amorphous silicon (a-Si) film on top of the SiNx or SiOx layer;

patterning the a-Si film to define an etch mask for the SiNx or SiOx layer;

removing the SiNx or SiOx layer via a Buffered Oxide Etch (BOE) chemical etch to expose the c-Si surface;

removing the a-Si mask with a hydrogen plasma etch in a PECVD tool to prevent current loss from the mask; and

plating the exposed c-Si surface with metal contacts, the metal contacts forming electrically conductive metallic pathways on a top surface of the photovoltaic cell.

18. The method of claim 17 , wherein depositing the amorphous silicon (a-Si) film on top of the SiNx or SiOx layer prepares the film for metallization without damaging the underlying crystalline silicon (c-Si) substrate.

19. The method of claim 17 :

wherein the a-Si film is susceptible to laser removal, but is non-reactive to the BOE chemical etch; and

wherein the layer formed from SiNx or SiOx is sensitive to the BOE chemical etch, but is not sensitive to the laser.

Assignments (2)
CONFIRMATORY LICENSE Recorded Oct 11, 2016
From: ARIZONA STATE UNIVERSITY, TEMPE
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 040315/0809 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2016
From: BAILLY, MARK SCOTT
To: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
Reel/Frame 039898/0322 →
Continuity (3)
Provisional Application 62286914 · Jan 25, 2016
Provisional Application 62244516 · Oct 21, 2015
Related Publication 20170117432A1 · Apr 27, 2017