IP Library Granted Patent US 9,741,663
Granted Patent B2
US 9,741,663 · App. 15/067,140 · Granted Aug 22, 2017

Semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 9,741,663
App. No.
15/067,140
Granted
Aug 22, 2017
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in an interconnect length direction. The device further includes an upper graphene layer formed on an upper face of the catalyst layer, and side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction.

Claims (43)

1. A semiconductor device comprising:

an underlayer formed on a substrate;

a catalyst layer disposed on the underlayer and extending in an interconnect length direction;

an upper graphene layer formed on an upper face of the catalyst layer; and

side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction,

wherein:

the upper graphene layer includes two side faces extending in the interconnect length direction, and each of the two side faces of the upper graphene layer includes a catalyst-noncontacting edge face that does not contact the catalyst layer,

an upper face of each of the side graphene layers includes a catalyst-noncontacting edge face that does not contact the catalyst layer, and

a side face that contacts the catalyst layer among side faces of each of the side graphene layers extending in the interconnect length direction includes a catalyst-contacting edge face that contacts the catalyst layer.

2. The device according to claim 1 , further comprising:

a liner layer formed between the underlayer and the catalyst layer.

3. The device according to claim 1 , further comprising:

a mask layer formed between the catalyst layer and the upper graphene layer.

4. The device according to claim 1 , further comprising:

a face seal layer that covers an uppermost face of the upper graphene layer.

5. The device according to claim 1 , further comprising:

an edge seal layer provided on at least one of the catalyst-noncontacting edge faces of the upper graphene layer and the catalyst-noncontacting edge face of at least one of the side graphene layers.

6. The device according to claim 1 , wherein:

the upper graphene layer includes one of halogen, metal halide, and alkali metal.

7. The device according to claim 1 , wherein:

each of the side graphene layers includes one of halogen, metal halide, and alkali metal.

8. The device according to claim 1 , further comprising:

a modifying layer provided on at least one of the catalyst-noncontacting edge faces of the upper graphene layer and the catalyst-noncontacting edge face of at least one of the side graphene layers.

9. The device according to claim 8 , wherein:

the modifying layer includes a modifying group having one of oxygen, nitrogen, and boron, and the modifying group modifies the catalyst-noncontacting edge face of the upper graphene layer and the catalyst-noncontacting edge face of the side graphene layer.

10. The device according to claim 1 , wherein:

the catalyst layer has a pillar shape, the upper face of the catalyst layer has a length that is substantially equal to a length of a bottom face of the catalyst layer in an interconnect width direction, and the two side faces of the catalyst layer are parallel to each other.

11. The device according to claim 1 , wherein:

each of the side graphene layers has an L-shape in which a side extending from the catalyst-contacting edge face of the side graphene layer in an interconnect width direction is connected with a side extending from the catalyst-noncontacting edge face of the side graphene layer in an interconnect height direction.

12. The device according to claim 1 , wherein:

the catalyst layer has a trapezoidal shape;

a length of the upper face of the catalyst layer is less than a length of a bottom face of the catalyst layer, in an interconnect width direction; and

the two side faces of the catalyst layer are inclined.

13. The device according to claim 1 , wherein:

each of the side graphene layers has an arc shape from the catalyst-contacting edge face to the catalyst-noncontacting edge face.

14. The device according to claim 1 , further comprising:

a contact via connected to an uppermost face of the upper graphene layer.

15. The device according to claim 1 , further comprising:

a contact via connected to the catalyst-noncontacting edge face one of of the side graphene layers and one of the two catalyst-noncontacting edge faces of the upper graphene layer.

16. The device according to claim 1 , further comprising:

a contact via connected to an uppermost face of the upper graphene layer, one of the two catalyst-noncontacting edge faces of the upper graphene layer, and the catalyst-noncontacting edge face of one of the two side graphene layers.

17. The device according to claim 1 , further comprising:

a contact via connected to an uppermost face of the upper graphene layer, and all of the catalyst-noncontacting edge faces of the upper graphene layer and the side graphene layers.

Assignments (4)
DE-MERGER Recorded Dec 12, 2019
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051260/0291 →
MERGER Recorded Dec 12, 2019
From: TOSHIBA MEMORY CORPORATION; K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051262/0776 →
CHANGE OF NAME AND ADDRESS Recorded Dec 12, 2019
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 051262/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2016
From: ISHIKURA, TAISHI; ISOBAYASHI, ATSUNOBU; SAITO, TATSURO; KAJITA, AKIHIRO; SAKAI, TADASHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 038101/0798 →