Wafer bonding edge protection using double patterning with edge exposure

1. A method of forming copper (Cu) interconnects in a wafer, the method comprising the steps of:

forming a dielectric layer on the wafer;

forming a first mask directly on the dielectric layer;

patterning the first mask with a footprint and location of the Cu interconnects, wherein the patterning of the first mask is performed over an entire surface of the wafer;

forming a second mask on, and in contact with, the first mask, wherein the second mask covers a portion of the patterned first mask at an edge region of the wafer;

patterning trenches in the dielectric layer through the first mask and the second mask, wherein the second mask blocks formation of the trenches at the edge region of the wafer and thereby provides edge protection during patterning of the trenches; and

forming the Cu interconnects in the trenches.

2. The method of claim 1 , wherein the edge region of the wafer comprises a portion of the wafer extending a distance x in from an outer circumference of the wafer towards a center of the wafer, wherein x is less than about 10 mm.

3. The method of claim 2 , wherein x is from about 1 mm to about 10 mm, and ranges therebetween.

4. The method of claim 1 , wherein the dielectric layer comprises a first dielectric layer on the wafer, and a second dielectric layer on the first dielectric layer.

5. The method of claim 4 , wherein the first dielectric layer comprises a nitride material and the second dielectric layer comprises an oxide material.

6. The method of claim 4 , wherein the step of forming the first mask on the dielectric layer comprises the steps of:

depositing an organic planarizing layer (OPL) on the second dielectric layer;

depositing an antireflective coating on the OPL; and

depositing a photoresist on the antireflective coating.

7. The method of claim 6 , wherein the step of patterning the first mask comprises the step of:

patterning the trenches in the photoresist and the antireflective coating.

8. The method of claim 6 , wherein the step of patterning the first mask comprises the step of:

patterning the photoresist, the antireflective coating, and the OPL to fully open the first mask to the second dielectric prior to forming the second mask.

9. The method of claim 4 , wherein the step of forming the first mask on the dielectric layer comprises the step of:

depositing a single layer of a photoresist on the second dielectric layer.

10. The method of claim 1 , wherein the step of forming the second mask on the first mask comprises the steps of:

depositing an OPL on the first mask, filling a pattern in the first mask;

depositing an antireflective coating on the OPL; and

depositing a negative tone develop (NTD) photoresist on the antireflective coating.

11. The method of claim 10 , further comprising the steps of:

developing the NTD photoresist such that the NTD photoresist remains covering only the edge region of the wafer; and

using the NTD photoresist covering the edge region of the wafer to open up the second mask such that the second mask covers only the edge region of the wafer.

12. The method of claim 1 , wherein the step of forming the second mask on the first mask comprises the step of:

depositing a single layer of an OPL on the first mask, filling a pattern in the first mask.

13. The method of claim 1 , wherein the step of forming the Cu interconnects in the trenches comprises the steps of:

plating Cu into the trenches;

performing a Cu edge bead removal process to remove Cu from the edge region of the wafer; and

planarizing the Cu to form the Cu interconnects in the trenches.

14. The method of claim 1 , further comprising the step of:

covering a bevel of the wafer with a shadow ring while patterning the trenches in the dielectric layer.

15. A wafer bonding method, comprising the steps of:

forming at least a first wafer by the steps of:

forming a dielectric layer on the wafer;

forming a first mask directly on the dielectric layer;

patterning the first mask with a footprint and location of the Cu interconnects, wherein the patterning of the first mask is performed over an entire surface of the wafer;

forming a second mask on, and in contact with, the first mask, wherein the second mask covers a portion of the patterned first mask at an edge region of the wafer;

patterning trenches in the dielectric layer through the first mask and the second mask, wherein the second mask blocks formation of the trenches at the edge region of the wafer and thereby provides edge protection during patterning of the trenches;

forming the Cu interconnects in the trenches;

depositing a first bonding oxide layer on the first wafer over the dielectric layer and the Cu interconnects; and

bonding the first wafer to a second wafer by wafer-to-wafer bonding, wherein the second wafer comprises a second bonding oxide layer, and wherein the wafer-to-wafer bonding comprises an oxide-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

16. The method of claim 15 , wherein the step of forming the first mask on the dielectric layer comprises the steps of:

depositing an OPL on the dielectric layer;

depositing an antireflective coating on the OPL; and

depositing a photoresist on the antireflective coating.

17. The method of claim 15 , wherein the step of forming the second mask on the first mask comprises the steps of:

depositing an OPL on the first mask, filling a pattern in the first mask;

depositing an antireflective coating on the OPL; and

depositing a NTD photoresist on the antireflective coating.

18. The method of claim 17 , further comprising the steps of:

developing the NTD photoresist such that the NTD photoresist remains covering only the edge region of the wafer; and

using the NTD photoresist covering the edge region of the wafer to open up the second mask such that the second mask covers only the edge region of the wafer.

19. The method of claim 15 , wherein the step of forming the Cu interconnects in the trenches comprises the steps of:

plating Cu into the trenches;

performing a Cu edge bead removal process to remove Cu from the edge region of the wafer; and

planarizing the Cu to form the Cu interconnects in the trenches.

20. The method of claim 15 , further comprising the step of:

covering a bevel of the wafer while patterning the trenches in the dielectric layer.