Array substrate, method for manufacturing the same, and display device
An array substrate comprises a TFT, a data line, a gate line and a passivation layer covering the TFT, the data line and the gate line. The array substrate further includes a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is disposed on the passivation layer and above the TFT, and the second conductive structure is disposed on the passivation layer and above the data line and/or gate line. A method for manufacturing the array substrate and a display device having such an array substrate are also provided.
1. An array substrate comprising a thin film transistor, a data line, a gate line and a passivation layer) disposed thereon, wherein the TFT comprises a gate electrode, a source electrode and a drain electrode, the data line is connected to the source electrode of the TFT, the gate line is connected to the gate electrode of the TFT, and the passivation layer covers the TFT, the data line and the gate line, and
wherein the array substrate further comprises a first conductive structure and a second conductive structure connected with the first conductive structure,
the first conductive structure is disposed in a display area of the array substrate and on the passivation layer and above the TFT, the second conductive structures disposed on the passivation layer and above at least one of the data line and the gate line.
2. The array substrate according to claim 1 , wherein the first conductive structure is connected to a ground terminal on the array substrate through the second conductive structure.
3. The array substrate according to claim 2 , wherein the first conductive structure and the second conductive structure comprise the same material as that of the pixel electrode.
4. The array substrate according to claim 2 , wherein each of the first conductive structure, the second conductive structure and the pixel electrode is made of ITO.
5. The array substrate according to claim 2 , wherein the array substrate further comprises a pixel electrode provided on the passivation layer.
6. The array substrate according to claim 2 , wherein the second conductive structure forms a charge discharge grid comprising a discharge row and a discharge column, and the discharge row is provided insulatedly in the region corresponding to the data line, and the discharge columns are provided insulatedly in the region corresponding to the gate line.
7. The array substrate according to claim 1 , wherein the array substrate further comprises a pixel electrode provided on the passivation layer.
8. The array substrate according to claim 7 , wherein, the pixel electrode is provided and isolated from the first conductive structure and the second conductive structure.
9. The array substrate according to claim 8 , wherein the pixel electrode, the first conductive structure and the second conductive structure are formed through one patterning process.
10. The array substrate according to claim 7 , wherein the pixel electrode, the first conductive structure and the second conductive structure are formed through one patterning process.
11. The array substrate according to claim 7 , wherein the first conductive structure and the second conductive structure comprise the same material as that of the pixel electrode.
12. The array substrate according to claim 7 , wherein each of the first conductive structure, the second conductive structure and the pixel electrode is made of ITO.
13. The array substrate according to claim 7 , wherein the second conductive structure forms a charge discharge grid comprising a discharge row and a discharge column, and the discharge row is provided insulatedly in the region corresponding to the data line, and the discharge columns are provided insulatedly in the region corresponding to the gate line.
14. The array substrate according to claim 1 , wherein the second conductive structure forms a charge discharge grid comprising a discharge row and a discharge column, and the discharge row is provided insulatedly in the region corresponding to the data line, and the discharge columns are provided insulatedly in the region corresponding to the gate line.
15. A display device comprising the array substrate according to claim 1 .
16. The display device according to claim 15 , wherein the display device further comprises an opposite substrate provided opposing the array substrate, and a spacer provided between the opposite substrate and the array substrate, and
at least a portion of the spacer is provided opposing to the first conductive structure.