Circuit for securing scan chain data

1. A circuit for protecting data in a scan chain, comprising:

a plurality of scan flip-flops coupled in a scan chain;

an input circuit configured to shift input the data to the scan flip-flops;

a protection circuit coupled to the scan flip-flops, the protection circuit configured to:

detect scan-in of the data from the input circuit to a designated one of the scan flip-flops;

enable scan-out of the data from the designated scan flip-flop in response to detection of the scan-in of the data from the input circuit to the designated scan flip-flop; and

disable scan-out of the data from the designated scan flip-flop in response to no detection of scan-in of the data from the input circuit to the designated scan flip-flop, wherein the protection circuit includes a linear feedback shift register (LFSR) configured to

shift the data from an output of one of the plurality of scan flip-flops, through scan registers of the LFSR, to an output node in response to scan-out being enabled by the protection circuit, and

block shifting out of the data from the one of the plurality of scan flip-flops to the output node in response to scan-out being disabled by the protection circuit.

2. The circuit of claim 1 , wherein

the LFSR is block shifting out of the data from the plurality of scan flip-flops to the output node by generating and outputting a pseudo-random sequence of data to the output node; and

the protection circuit is directly coupled between two of the scan flip-flops in the scan chain, and wherein the data input to the scan flip-flops is in one of said two of the scan flip-flops in the scan chain.

3. The circuit of claim 2 , wherein the protection circuit includes a plurality of scan flip-flops in the scan chain.

4. The circuit of claim 3 , wherein the protection circuit further comprises:

a detector circuit coupled to the plurality of scan flip-flops of the protection circuit, wherein the detector circuit is configured to:

detect whether or not a scan-in of the data from the input circuit to the designated scan flip-flop has occurred; and

generate an enable signal having a state that indicates whether or not a scan-in of the data from the input circuit to the designated scan flip-flop has occurred.

5. The circuit of claim 4 , wherein the protection circuit further comprises:

a data blocker circuit coupled to the detector circuit and coupled to the plurality of scan flip-flops of the protection circuit, wherein the data blocker is configured to block shifting out of the data from the plurality of scan flip-flops in the protection circuit in response to the enable signal having a state that indicates that a scan-in of the data from the input circuit to the designated scan flip-flop has not occurred.

6. The circuit of claim 4 , wherein the linear feedback shift register (LFSR) is coupled to the detector circuit and coupled to the plurality of scan flip-flops of the protection circuit, wherein the LFSR is configured to:

block shifting out of the data from the plurality of scan flip-flops in the protection circuit in response to the enable signal having a state that indicates that a scan-in of the data from the input circuit to the designated scan flip-flop has not occurred; and

shift out the data from the plurality of scan flip-flops in the protection circuit in response to the enable signal having a state that indicates that a scan-in of the data from the input circuit to the designated scan flip-flop has occurred.

7. The circuit of claim 1 , wherein:

the protection circuit includes a plurality of scan flip-flops in the scan chain directly coupled between two of the scan flip-flops in the scan chain, and the protection circuit includes:

a sequence detector configured to detect a particular value scanned-in to the scan flip-flops in the protection circuit and generate an enable signal in a first state in response to detection of the particular value, and generate the enable signal in a second state in response to no detection of the particular value; and

a data blocker coupled to receive the enable signal from the sequence detector, the data blocker configured to enable shifting out of the data from the scan flip-flops in the protection circuit in response to the enable signal being in the first state, and configured to block shifting out of the data from the scan flip-flops in the protection circuit in response to the enable signal being in the second state.

8. The circuit of claim 7 , wherein the linear feedback shift register (LFSR) is coupled to receive the enable signal and coupled to the scan flip-flops of the protection circuit, wherein the LFSR is configured to:

block shifting out of the data from the plurality of scan flip-flops in the protection circuit in response to the enable signal being in the first state; and

shift out the data from the plurality of scan flip-flops in the protection circuit in response to the enable signal being in the second state.

9. The circuit of claim 1 , wherein the LFSR includes a set of scan registers, each having a respective data input node, a respective test input node, a respective output node, and a respective test enable node and configured to use the data input node for inputting data when the respective test enable node is set to a first value and use the test input node for inputting data when the respective test enable node is set to a second value.

10. The circuit of claim 9 , wherein the set of scan registers are interconnected to form a shift register when the test enable nodes are set to the second value, and form a pseudo-random number generator when test enable nodes are set to the first value.

11. A circuit for protecting data in a scan chain, comprising:

a plurality of intermediate scan flip-flops directly coupled between two scan flip-flops in the scan chain;

a detector circuit coupled to the intermediate scan flip-flops, the detector circuit configured to:

detect a particular value scanned-in to the intermediate scan flip-flops,

generate an enable signal in a first state in response to detection of the particular value, and

generate the enable signal in a second state in response to no detection of the particular value; and

a data blocker circuit coupled to the detector circuit and to the intermediate scan flip-flops, the data blocker circuit configured to:

enable shifting out of data from the intermediate scan flip-flops in response to the enable signal being in the first state, and

disable shifting out of the data from the intermediate scan flip-flops in response to the enable signal being in the second state, and

a linear feedback shift register (LFSR) coupled to the detector circuit and configured to

shift the data from an output of one of the plurality of scan flip-flops, through scan registers of the LFSR, to an output node in response to scan-out being enabled by the protection circuit, and

block shifting out of the data from the one of the plurality of scan flip-flops to the output node in response to scan-out being disabled by the protection circuit.

12. The circuit of claim 11 , wherein the LFSR is configured to block the shifting out of the data from the plurality of scan flip-flops to the output node by generating and outputting a pseudo-random sequence of data to the output node.

13. A method of protecting data in a scan chain, comprising:

scanning-in data as the data are being scanned out from the scan chain;

monitoring for a scan-in of the data from an initial scan flip-flop in the scan chain to a designated scan flip-flop in the scan chain;

in response to no detection of scan-in of the data from the initial scan flip-flop to the designated scan flip-flop, disable scan-out of the data from the designated scan flip-flop by setting a linear feedback shift register (LFSR) to prevent the data from being shifted through the LFSR to an output node; and

in response to detection of a scan-in of the data from the initial scan flip-flop to the designated scan flip-flop, enabling scan-out of the data from the designated scan flip-flop by setting the LFSR to shift the data through the LFSR to an output node.

14. The method of claim 13 , wherein:

the enabling of scan-out of the data includes shifting the data from the designated scan flip-flop through a plurality of scan flip-flops, and selecting scan-in data to input to the plurality of scan flip-flops in response to detection of scan-in of the data from the initial scan flip-flop to the designated scan flip-flop; and

the disabling of scan-out of the data includes selecting linear feedback data to input to the plurality of scan flip-flops in response to a scan-in of the data from the initial scan flip-flop to the designated scan flip-flop not having been detected.

15. The method of claim 13 , further comprising:

shifting the data from the designated scan flip-flop through a plurality of intermediate scan flip-flops; and

the monitoring includes comparing bit values in the intermediate scan flip-flops to a programmed value.

16. The method of claim 15 , further comprising:

enabling scan-out of the data from the designated scan flip-flop in response to bit values in the intermediate scan flip-flops being equal to the programmed value; and

blocking scan-out of the data in response to bit values in the intermediate scan flip-flops being not equal to the programmed value.

17. The method of claim 13 , wherein the blocking scan-out of the data includes shifting pseudo-random data through the scan chain beginning at the designated scan flip-flop.

18. The method of claim 13 , wherein the blocking scan-out of the data includes shifting logic 0 values through the scan chain beginning at the designated scan flip-flop.

19. The method of claim 13 , wherein the blocking scan-out of the data includes shifting logic 1 values through the scan chain beginning at the designated scan flip-flop.