Multi-threshold voltage structures with a lanthanum nitride film and methods of formation thereof
Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.
1. A semiconductor device having a multi-threshold voltage structure, comprising:
a substrate;
a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer;
a lanthanum nitride layer deposited atop the high-k dielectric layer;
an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and
a gate electrode layer atop the lanthanum nitride layer.
2. The semiconductor device of claim 1 , wherein the lanthanum nitride layer has a thickness of about 3 angstroms.
3. The semiconductor device of claim 1 , wherein the lanthanum nitride layer is about 10 to about 50 atomic percent nitrogen and the balance lanthanum.
4. The semiconductor device of claim 1 , wherein the high-k dielectric layer is hafnium oxide or hafnium silicate.
5. The semiconductor device of claim 1 , wherein the gate electrode layer is titanium nitride.
6. A method of forming a semiconductor device having a multi-threshold voltage structure, comprising:
depositing a lanthanum nitride layer atop a substrate comprising a gate dielectric layer, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer;
depositing a gate electrode layer atop the lanthanum nitride layer;
depositing a capping layer atop the gate electrode layer; and
annealing the substrate to a temperature of about 700 to about 950 degrees Celsius to diffuse lanthanum species from the lanthanum nitride layer to an interface of the interface layer and the high-k dielectric layer.
7. The method of claim 6 , further comprising:
patterning the semiconductor device to form a film stack atop the substrate; and
forming a source/drain region atop the substrate.
8. The method of claim 6 , wherein the lanthanum nitride layer has a thickness of about 3 angstroms.
9. The method of claim 6 , wherein the lanthanum nitride layer is about 10 to about 50 atomic percent nitrogen and the balance lanthanum.
10. The method of claim 6 , wherein the high-k dielectric layer is hafnium oxide or hafnium silicate.
11. The method of claim 6 , wherein the gate electrode layer is titanium nitride.
12. The method of claim 6 , wherein the lanthanum nitride layer is deposited via an atomic layer deposition process.
13. The semiconductor device of claim 1 , further comprising a capping layer deposited atop the gate electrode layer for protecting the gate electrode layer from processing.
14. The semiconductor device of claim 13 , wherein the capping layer is polysilicon.
15. The semiconductor device of claim 1 , wherein the high-k dielectric layer comprises a dielectric material having a dielectric constant greater than about 4.
16. The semiconductor device of claim 1 , wherein the substrate comprises a p-type region, and wherein the gate dielectric layer is disposed atop at least part of the p-type region.
17. The semiconductor device of claim 16 , wherein the p-type region has a doping density of between about 5×10 16 atoms/cm 3 and about 5×10 19 atoms/cm 3 .
18. The semiconductor device of claim 16 , wherein the substrate further comprises first and second source/drain regions, the first source/drain region disposed on a first side of the gate dielectric layer and the second source/drain region disposed on a second side of the gate dielectric layer.
19. The semiconductor device of claim 16 , further comprising first and second sidewall spacers comprising insulating material, wherein the first sidewall spacer is formed along a first outer sidewall of a film stack comprising the gate dielectric layer, the lanthanum nitride layer, the interface layer, and the gate electrode layer, and wherein the second sidewall spacer is formed along a second outer sidewall of the film stack.
20. A non-transitory computer readable medium, having instructions stored thereon that, when executed, cause a method of forming a semiconductor device having a multi-threshold voltage structure, the method comprising:
depositing a lanthanum nitride layer atop a substrate comprising a gate dielectric layer, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer;
depositing a gate electrode layer atop the lanthanum nitride layer;
depositing a capping layer atop the gate electrode layer; and
annealing the substrate to a temperature of about 700 to about 950 degrees Celsius to diffuse lanthanum species from the lanthanum nitride layer to an interface of the interface layer and the high-k dielectric layer.