Active matrix light emitting diodes display module with carbon nanotubes control circuits and methods of fabrication

1. A method of forming active matrix single-walled carbon nanotubes control circuits integrated on light-emitting diode pixels, comprising the steps of:

forming an N-COM layer on an light-emitting diode wafer;

forming an insulation layer over the N-COM layer;

forming a single-walled carbon nanotubes thin film on the insulation layer;

forming a plurality of source and drain contacts on the single-walled carbon nanotubes thin film;

patterning an active single-walled carbon nanotubes thin film;

forming source and drain electrodes over the active single-walled carbon nanotubes thin film;

forming a dielectric layer over the source/drain layer;

patterning a plurality of Via holes in the dielectric layer; and

forming a gate layer and a Via electrode over the dielectric layer.

2. The method of claim 1 , wherein the N-COM layer comprises nickel/gold and has a thickness of 300 nm-500 nm and line width in the range of 100 nm-20 μm.

3. The method of claim 2 , wherein the forming the N-COM layer comprises:

spin coating a photoresist layer on an LED wafer;

defining a pattern by photolithography to generate regions of a defined photoresist;

solution developing the defined pattern into a developed photoresist;

depositing a Ni/Au layer on the developed photoresist by one of sputtering and evaporation; and lifting-off the developed photoresist.

4. The method of claim 1 , wherein the insulation layer comprises one of SiO 2 and Si 3 N 4 with a thickness of 300˜500 nm.

5. The method of claim 4 , wherein the forming the insulation layer comprises depositing SiO 2 or Si 3 N 4 over the N-COM layer uses one of plasma chemical vapor deposition and low pressure chemical vapor deposition.

6. The method of claim 1 , wherein the single-walled carbon nanotubes layer comprises 65 single-walled carbon nanotubes in a layer with a thickness of 10-20 nm.

7. The method of claim 6 , wherein the forming the single-walled carbon nanotubes layer comprises:

solution depositing polyamines over the insulation layer for 5 minutes to 24 hours; and

solution depositing the 65 single-walled carbon nanotubes over the polyamines for 5 minutes to 24 hours.

8. The method of claim 7 , wherein the polyamines comprises a poly-L-lysine aqueous solution.

9. The method of claim 6 , wherein the forming the single-walled carbon nanotubes layer comprises:

printing the 65 single-walled carbon nanotubes over the insulation layer; and

treating the 65 single-walled carbon nanotubes with acetic acid vapor for 10 minutes to 24 hours.

10. The method of claim 9 , wherein the 65 single-walled carbon nanotubes is selected from the group including screen printing, inkjet printing, aerosol jet printing, roll-to-roll gravure, and flexography.

11. The method of claim 1 , wherein the plurality of source and drain contacts comprises gold with a thickness of 10 nm-50 nm.

12. The method of claim 11 , wherein the forming the source and drain contacts further comprises:

spin coating a photoresist layer on the single-walled carbon nanotubes layer;

defining a pattern by photolithography to create regions of defined photoresist;

solution developing the defined pattern to form a developed photoresist;

depositing Au on the developed photoresist layer; and

lifting-off the developed photoresist.

13. The method of claim 1 , wherein the patterning the active single-walled carbon nanotubes thin film further comprises:

spin coating a photoresist on the single-walled carbon nanotubes thin film;

defining a pattern by photolithography to create regions of a defined photoresist and undefined photoresist;

solution developing the defined pattern to form a developed photoresist; and

plasma etching the single-walled carbon nanotubes thin film using the developed photoresist.

14. The method of claim 1 , wherein the source and drain electrodes comprise chromium/gold and has a thickness of 300 nm˜500 nm and line width of 100 nm˜20 μm.

15. The method of claim 14 , wherein the forming the source and drain electrodes further comprises:

spin coating a photoresist layer on the single-walled carbon nanotubes layer;

defining a pattern by photolithography to create regions of defined photoresist and undefined photoresist;

solution developing the defined pattern to form a developed photoresist;

depositing chromium/gold on the developed photoresist layer by one of sputtering and evaporation; and

lifting-off the developed photoresist.

16. The method of claim 1 , wherein the dielectric layer comprises SiO 2 or Si 3 N 4 and has a thickness in the range of 50 nm-500 nm.

17. The method of claim 16 , wherein the dielectric layer is formed by depositing SiO 2 or Si 3 N 4 over the source and drain electrodes using plasma chemical vapor deposition or low pressure chemical vapor deposition.

18. The method of claim 1 , wherein the patterning Via holes comprises:

spin coating a photoresist on the dielectric layer;

defining a pattern by photolithography to create regions of a defined photoresist;

solution developing the defined pattern to form a developed photoresist; and

dry or wet etching the developed dielectrics using the developed photoresist.

19. The method of claim 1 , wherein the gate layer and the Via contact comprises chromium/gold and has a thickness of 300 nm˜500 nm and line width of 100 nm˜20 μm.

20. The method of claim 19 , wherein the forming gate layer and Via contact comprises:

spin coating a photoresist layer on the dielectric layer;

defining a pattern by photolithography to create regions of a defined photoresist and undefined photoresist;

developing the defined photoresist pattern;

depositing Cr/Au on the developed photoresist layer by one of sputtering and evaporation; and

lifting-off the developed photoresist.