Backside fib probing detector in a forward and reverse body biasing architecture

1. An integrated circuit comprising a plurality of first semiconductor strips of a first conductivity type and a plurality of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, comprising for each of the first semiconductor strips:

a plurality of bias contacts;

a plurality of switches, wherein each switch is associated with a respective bias contact, each switch capable of applying a potential on the respective bias contact;

two detection contacts arranged at ends of the first semiconductor strip; and

a detection circuit configured to control the switches and to compare a resistance between the detection contacts with a reference threshold.

2. The integrated circuit of claim 1 , wherein the reference threshold is a normal resistance of a first semiconductor strip between the detection contacts.

3. The integrated circuit of claim 1 , wherein each detection circuit is configured to apply a bias potential to one of the detection contacts of the associated first semiconductor strip.

4. The integrated circuit of claim 1 , wherein a detection circuit is common to two first semiconductor strips, the reference threshold associated with a first semiconductor strip being the resistance between the detection contacts of the other first semiconductor strip.

5. The integrated circuit of claim 1 , wherein, for each first semiconductor strip, the switches are MOS transistors formed inside of and on a first semiconductor strip next to the first semiconductor strip.

6. The integrated circuit of claim 1 , wherein the detection circuit associated with a first semiconductor strip comprises MOS-type transistors formed inside of and on a first semiconductor strip next to the first semiconductor strip.

7. The integrated circuit of claim 1 , wherein each detection circuit is capable of applying a voltage between 300 and 500 mV between the detection contacts of the associated first semiconductor strip.

8. The integrated circuit of claim 1 , wherein a width of the first semiconductor strips and of the second semiconductor strips is smaller than 2.5 μm and a length of the first semiconductor strips and of the second semiconductor strips is greater than 100 μm.

9. The integrated circuit of claim 1 , wherein the integrated circuit has a total surface area, the first and second semiconductor strips, the switches and the detection circuits taking up less than 1% of the total surface area.

10. The integrated circuit of claim 1 , wherein the detection circuits are successively activated, a single detection circuit being activated at a time.

11. An integrated circuit comprising:

a semiconductor substrate having a first conductivity type;

a semiconductor layer overlying the semiconductor substrate and having a second conductivity type opposite the first conductivity type;

a semiconductor region overlying the semiconductor layer, the semiconductor region including a plurality of n-doped strips interdigitated with a plurality of p-doped strips;

a plurality of bias contacts disposed within the semiconductor region;

a plurality of switches, wherein each switch is associated with a respective bias contact, each switch capable of applying a potential on the respective bias contact;

a plurality of detection contacts arranged at ends of strips that include bias contacts; and

a plurality of detection circuits, each detection circuit configured to control at least one associated switch and to compare a resistance between the detection contacts of the associated strip with a reference threshold.

12. The integrated circuit of claim 11 , wherein VDD bias contacts are disposed within the n-doped strips and wherein ground bias contacts are disposed within the p-doped strips.

13. The integrated circuit of claim 12 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

14. The integrated circuit of claim 11 , wherein the switches comprise MOS transistors.

15. The integrated circuit of claim 11 , wherein each detection circuit is configured to apply a voltage in between 300 and 500 mV between the detection contacts of the associated strip.

16. The integrated circuit of claim 11 , wherein each strip has a width that is smaller than 2.5 μm and a length that is greater than 100 μm.

17. The integrated circuit of claim 11 , wherein the detection circuits are successively activated, a single detection circuit being activated at a time.

18. An integrated circuit, comprising:

a plurality of first semiconductor strips of a first conductivity type;

a plurality of second semiconductor strips of a second conductivity type interdigitated with the plurality of first semiconductor strips, wherein each of the first semiconductor strips comprises:

a first detection contact at a first end of the first semiconductor strip;

a second detection contact at a second end of the first semiconductor strip;

a bias contact disposed between the first detection contact and the second detection contact along a length-wise direction of the first semiconductor strip; and

a switch coupled between the bias contact and a bias potential; and

a detection circuit configured to determine a resistance of the first semiconductor strip between the first detection contact and the second detection contact based on a test signal.

19. The integrated circuit of claim 18 , the detection circuit being further configured to compare the resistance against a reference threshold.

20. The integrated circuit of claim 18 , the switch being configured to decouple the bias contact from the bias potential when the detection circuit determines the resistance.

21. The integrated circuit of claim 18 , wherein the test signal comprises a voltage between 300 and 500 mV.

22. The integrated circuit of claim 18 , wherein the bias potential comprises a ground potential.