Single spacer for complementary metal oxide semiconductor process flow
A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.
1. A semiconductor device comprising:
p-type FinFETs in a first device region and n-type FinFETs in a second device region of a substrate;
a gate structure present on a channel portion for each of the fin structures for each of the p-type and n-type FinFETs;
gate sidewall spacers of a low-k dielectric material present on the gate structures for each of the n-type FinFETs and the p-type FinFETs, wherein the gate sidewall spacers for each of the n-type and p-type FinFETs have substantially a same width; and
source and drain epitaxial semiconductor material on the fin structures for each of the p-type FinFETs and the n-type FinFETs, wherein an oxide surface liner is present on exterior surfaces of the source and drain epitaxial semiconductor material of the p-type FinFETs that is not present on exterior surfaces of the source and drain epitaxial semiconductor material of the n-type FinFETs.
2. The semiconductor device of claim 1 , wherein the gate sidewall spacers for the n-type finFETs comprise a high-k dielectric fin liner material present at an interface of the gate sidewall spacers, and the fin structures.
3. The semiconductor device of claim 1 , wherein the low-k dielectric material of the gate sidewall spacers is SiOCN.
4. The semiconductor device of claim 1 , wherein the source and drain epitaxial semiconductor material for the p-type FinFETs are composed of a germanium containing material.
5. The semiconductor device of claim 4 , wherein the oxide surface liner is germanium oxide.
6. The semiconductor device of claim 5 , wherein the germanium oxide has a thickness ranging from 1 nm to 10 nm.
7. The semiconductor device of claim 1 , wherein the source and drain regions for the n-type FinFETs are composed of an epitaxial silicon material.
8. The semiconductor device of claim 1 , wherein the source and drain regions for the n-type FinFETs are composed of an epitaxial silicon doped with carbon material.
9. A semiconductor device comprising:
p-type FinFETs in a first device region and n-type FinFETs in a second device region of a substrate;
a gate structure present on a channel portion for each of the fin structures for each of the p-type and n-type FinFETs;
gate sidewall spacers of a low-k dielectric material present on the gate structures for each of the n-type FinFETs and the p-type FinFETs, wherein the gate sidewall spacers for each of the n-type and p-type FinFETs have substantially a same width, wherein the gate sidewall spacers for the n-type finFETs comprise a high-k dielectric fin liner material present at an interface of the gate sidewall spacers, and the fin structures; and
source and drain epitaxial semiconductor material on the fin structures for each of the p-type FinFETs and the n-type FinFETs, wherein an oxide surface liner is present on exterior surfaces of the source and drain epitaxial semiconductor material of the p-type FinFETs that is not present on exterior surfaces of the source and drain epitaxial semiconductor material of the n-type FinFETs.
10. The semiconductor device of claim 9 , wherein the low-k dielectric material of the gate sidewall spacers is SiOCN.
11. The semiconductor device of claim 9 , wherein the source and drain epitaxial semiconductor material for the p-type FinFETs is composed of an epitaxial germanium containing material.
12. The semiconductor device of claim 9 , wherein the oxide surface liner is germanium oxide.
13. The semiconductor device of claim 12 , wherein the germanium oxide has a thickness ranging from 1 nm to 10 nm.
14. The semiconductor device of claim 12 , wherein the germanium oxide has a thickness ranging from 1 nm to 10 nm.
15. The semiconductor device of claim 1 , wherein the source and drain epitaxial semiconductor material for the n-type FinFETs is composed of an epitaxial silicon material or epitaxial silicon doped with carbon material.
16. A semiconductor device comprising:
p-type FinFETs in a first device region and n-type FinFETs in a second device region of a substrate;
a gate structure present on a channel portion for each of the fin structures for each of the p-type and n-type FinFETs;
gate sidewall spacers of a low-k dielectric material present on the gate structures for each of the n-type FinFETs and the p-type FinFETs, wherein the gate sidewall spacers for each of the n-type and p-type FinFETs have substantially a same width, wherein the gate sidewall spacers for the n-type finFETs comprise a high-k dielectric fin liner material present at an interface of the gate sidewall spacers, and the fin structures; and
source and drain regions for the p-type FinFETs comprised of an epitaxial germanium containing material having an exterior surface that is oxidized, wherein an exterior surface of source and drains regions for the n-type FinFETs is not oxidized.
17. The semiconductor device of claim 16 , wherein the low-k dielectric material of the gate sidewall spacers is SiOCN.
18. The semiconductor device of claim 16 , wherein the exterior surface of the epitaxial germanium containing material is germanium oxide.