Semiconductor device and manufacturing method thereof
A semiconductor device includes a first n− type layer and a second n− type layer that are sequentially disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench that are disposed at the second n− type layer and are spaced apart from each other; a p type region surrounding a lateral surface and a lower surface of the first trench; an n+ type region disposed on the p type region and the second n− type layer; a gate insulating layer disposed in the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ type region disposed in the first trench; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate.
1. A semiconductor device comprising:
a first n− type layer and a second n− type layer that are sequentially disposed on a first surface of an n+ type silicon carbide substrate;
a first trench and a second trench that are disposed at the second n− type layer and are spaced apart from each other;
a p type region that surrounds a lateral surface and a lower surface of the first trench;
an n+ type region that is disposed on the p type region and the second n− type layer;
a gate insulating layer disposed in the second trench;
a gate electrode disposed on the gate insulating layer;
an oxide layer disposed on the gate electrode;
a source electrode that is disposed on the oxide layer and the n+ type region and that is disposed in the first trench; and
a drain electrode that is disposed at a second surface of the n+ type silicon carbide substrate.
2. The semiconductor device of claim 1 , wherein
a doping concentration of the second n− type layer is different from that of the first n− type layer.
3. The semiconductor device of claim 2 , wherein
the second n− type layer is disposed between the second trench and the p type region.
4. The semiconductor device of claim 3 , further comprising:
a p+ type region disposed between the p type region and the lower surface of the first trench.
5. The semiconductor device of claim 4 , wherein
the source electrode contacts the p+ type region disposed under the first trench.
6. The semiconductor device of claim 1 , wherein
each of the source electrode and the drain electrode includes an ohmic metal.
7. The semiconductor device of claim 1 , wherein
a doping concentration of the second n− type layer is equal to that of the first n− type layer.
8. A manufacturing method of a semiconductor device, the manufacturing method comprising:
sequentially forming a first n− type layer and a second n− type layer on a first surface of an n+ type silicon carbide substrate;
forming an n+ type region on the second n− type layer;
forming a first trench and a second trench spaced apart from each other by etching the n+ type region and the second n− type layer;
forming a p type region to surround a lateral portion and a lower portion of the first trench;
forming a p+ type region between the lower surface of the first trench and the p type region;
forming a gate insulating layer in the second trench;
forming a gate electrode on the gate insulating layer;
forming an oxide layer on the gate electrode;
forming a source electrode on the oxide layer and the n+ type region, and in the first trench; and
forming a drain electrode at a second surface of the n+ type silicon carbide substrate,
wherein the source electrode contacts the p+ type region disposed under the first trench.
9. The manufacturing method of claim 8 , wherein
a doping concentration of the second n− type layer is different from that of the first n− type layer.
10. The manufacturing method of claim 9 , wherein in the forming of the p type region,
p ions are injected by tilt ion injection.
11. The manufacturing method of claim 8 , wherein
a doping concentration of the second n− type layer is equal to that of the first n− type layer.