Laminated structures for power efficient on-chip magnetic inductors

1. A method of making a laminated magnetic structure comprising:

depositing, over a supporting substrate, a first sequence of layers comprising, in order, a barrier layer or an adhesion layer, a first antiferromagnetic layer, a first magnetic growth layer, and a first soft magnetic layer;

depositing an insulating non-magnetic spacer located between the first sequence of layers and a second sequence of layers;

depositing the second sequence of layers comprising, in order, a second soft magnetic layer, a second magnetic growth layer, and a second antiferromagnetic layer; and

pinning the first and second soft magnetic layers with, respectively, the first and second antiferromagnetic layers by subjecting the layers to annealing in a magnetic field;

wherein the first soft magnetic layer is directly deposited on a surface of the first magnetic growth layer, and wherein the second magnetic growth layer is directly deposited on a surface of the second soft magnetic layer.

2. The method of claim 1 , wherein the second antiferromagnetic layer is directly deposited on a surface of the second magnetic growth layer.

3. The method of claim 1 , wherein the first and second antiferromagnetic layers are independently formed by depositing an alloy of manganese, an alloy comprising platinum and manganese, an alloy comprising iron and manganese, and an alloy comprising nickel and manganese.

4. The method of claim 1 , wherein the first and second soft magnetic layers are formed by depositing a material comprising an element selected from the group consisting of CoFeB, CoWB, CoWP, CoP, CoMoP, CoMoB, NiFe, NiFeCo, and NiFeCo, and combinations thereof.

5. The method of claim 1 , wherein the layers are deposited by sputtering.