IP Library › Granted Patent US 9,779,058
Granted Patent B2
US 9,779,058 · App. 14/854,787 · Granted Oct 3, 2017

Modulating processsor core operations

Inventor: Luiz Andre Barroso (Los Altos Hills, CA)
Assignee: Google Inc.
G06F15/80G06F9/5061
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,779,058
App. No.
14/854,787
Filed
Sep 15, 2015
Granted
Oct 3, 2017
Kind
B2
Art Unit
2115
USPC
713/300
Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reducing processor latency through the use of dedicated cores. In one aspect, a method includes a multi-core processor having n cores, including, selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, m cores are unselected, and each core of the multi-core processor has a rated core capacity. The methods operate the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity and operate one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.

Claims (54)

1. A method implemented in a multi-core processor having n cores, comprising:

selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, wherein:

k is less than n;

m cores are unselected; and

each core of the multi-core processor has a rated core capacity;

operating the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity; and

operating one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores, and wherein selections of the k cores in the multi-core processor are periodically rotated such that at each selection a different set of k cores are selected.

2. The method of claim 1 , wherein operating one or more of the m cores at a capacity in excess of the rated core capacity comprises operating the one or more of the m cores at a capacity that does not exceed a sum of m rated core capacities and the underutilized capacity.

3. The method of claim 1 , wherein operating one or more of the m cores at a capacity in excess of the rated core capacity comprises operating the one or more of the m cores at a capacity that temporarily exceeds a sum of m rated core capacities and the underutilized capacity.

4. The method of claim 1 , wherein:

the multi-core processor has a processor rated capacity; and

operating one or more of the m cores at a capacity in excess of the rated core capacity comprises operating the one or more of the m cores at capacities such that a sum of the capacities at which the m cores are operating and a sum of the capacities at which the k cores are operating does not exceed the processor rated capacity.

5. The method of claim 1 , wherein the rated core capacity is a rated core operational frequency.

6. The method of claim 1 , wherein the rated core capacity is a rated core power consumption.

7. The method of claim 1 , wherein k+m is equal to n.

8. The method of claim 1 , wherein the dedicated low-latency operations include at least one of memory accessing operations, I/O operations, and inter-processor communication.

9. A method implemented in a multi-core processor having n cores, comprising:

selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, wherein:

k is less than n;

m cores are unselected;

each core of the multi-core processor has a rated core capacity; and

the multi-core processor has a processor rated capacity, wherein the processor rated capacity is less than a sum of the rated core capacities of the n cores;

operating the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity;

operating one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores; and

operating one or more of the m cores at a capacity in excess of the rated core capacity comprises operating the one or more of the m cores at capacities such that a sum of the capacities at which the m cores are operating and a sum of the capacities at which the k cores are operating does not exceed the processor rated capacity.

10. A method implemented in a multi-core processor having n cores, comprising:

selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, wherein:

k is less than n;

m cores are unselected; and

each core of the multi-core processor has a rated core capacity, wherein the rated core capacity is a rated core operational temperature;

operating the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity; and

operating one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.

11. A non-transitory storage medium in data communication with a multi-core processor having n cores and storing instructions that cause the multi-core processor to perform operations comprising:

selecting k cores of the n-cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, and m cores are unselected, and wherein each core of the multi-core processor has a rated core capacity;

operating the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity and periodically rotating selections of the k cores in the multi-core processor; and

operating one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.

12. The non-transitory storage medium of claim 11 , wherein operating one or more of the m cores at a capacity in excess of the rated core capacity comprises operating the one or more of the m cores at a capacity that does not exceed a sum of m rated core capacities and the underutilized capacity.

13. The non-transitory storage medium of claim 11 , wherein operating one or more of the m cores at a capacity in excess of the rated core capacity comprises operating the one or more of the m cores at a capacity that temporarily exceeds a sum of m rated core capacities and the underutilized capacity.

14. The non-transitory storage medium of claim 11 , wherein:

the multi-core processor has a processor rated capacity; and

operating one or more of the m cores at a capacity in excess of the rated core capacity comprises operating the one or more of the m cores at capacities such that a sum of the capacities at which the m cores are operating and a sum of the capacities at which the k cores are operating does not exceed the processor rated capacity.

15. The non-transitory storage medium of claim 11 , wherein the rated core capacity is a rated core operational frequency.

16. The non-transitory storage medium of claim 11 , wherein the rated core capacity is a rated core power consumption.

17. The non-transitory storage medium of claim 11 , wherein k+m is equal to n.

18. The non-transitory storage medium of claim 11 , wherein the dedicated low-latency operations include at least one of memory accessing operations, I/O operations, and inter-processor communication.

19. A non-transitory storage medium in data communication with a multi-core processor having n cores and storing instructions that cause the multi-core processor to perform operations comprising:

selecting k cores of the n-cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, and m cores are unselected, and wherein each core of the multi-core processor has a rated core capacity, and the multi-core processor has a processor rated capacity, wherein the processor rated capacity is less than a sum of the rated core capacities of the n cores;

operating the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity;

operating one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores; and

operating one or more of the m cores at a capacity in excess of the rated core capacity comprises operating the one or more of the m cores at capacities such that a sum of the capacities at which the m cores are operating and a sum of the capacities at which the k cores are operating does not exceed the processor rated capacity.

20. A non-transitory storage medium in data communication with a multi-core processor having n cores and storing instructions that cause the multi-core processor to perform operations comprising:

selecting k cores of the n-cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, and m cores are unselected, and wherein each core of the multi-core processor has a rated core capacity;

operating the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity, wherein the rated core capacity is a rated core operational temperature; and

operating one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.

Assignments (2)
CHANGE OF NAME Recorded Oct 5, 2017
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 044129/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2015
From: BARROSO, LUIZ ANDRE
To: GOOGLE INC.
Reel/Frame 036573/0507 →
Continuity (2)
Provisional Application 62191763 · Jul 13, 2015
Related Publication 20170017611A1 · Jan 19, 2017