Gate drive circuit, cascade gate drive circuit and method for driving cascade gate drive circuit

1. A gate drive circuit, comprising a driving transistor and a switching transistor, wherein

the switching transistor comprises a gate electrode, a first electrode, and second electrode, wherein

the gate electrode is configured to receive a first switching signal,

the first electrode of the switching transistor is configured to receive a second switching signal, and

the second electrode of the switching transistor is electrically connected to a gate electrode of the driving transistor; and

the driving transistor comprises a first electrode and a second electrode, wherein

the first electrode of the driving transistor is configured to receive a first control signal, and

the second electrode of the driving transistor is electrically connected to an output terminal; and, wherein

during a display period, the first control signal is a display scanning signal, the first switching signal switches the switching transistor off, the driving transistor is switched on upon reception of a display switching signal, and the driving transistor outputs the display scanning signal; and

during a touch-control period, the first control signal is a touch scanning signal, the first switching signal switches the switching transistor on, the second switching signal switches the driving transistor on, and the driving transistor outputs the touch scanning signal.

2. The gate drive circuit according to claim 1 , further comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor and a second capacitor, wherein

a gate electrode of the first transistor is configured to receive a first switch-on signal, a first electrode of the first transistor is configured to receive a first power supply signal, and a second electrode of the first transistor and the gate electrode of the driving transistor are both electrically connected to a first node;

a gate electrode of the second transistor is configured to receive a second switch-on signal, a first electrode of the second transistor is configured to receive a second power supply signal, and a second electrode of the second transistor and the gate electrode of the driving transistor are both electrically connected to the first node;

a gate electrode of the third transistor and a gate electrode of the fifth transistor are both connected to a second node, a first electrode of the third transistor is configured to receive a first constant potential signal, and a second electrode of the third transistor is electrically connected to the first node;

a gate electrode of the fourth transistor is electrically connected to the first node, a first electrode of the fourth transistor is configured to receive the first constant potential signal, and a second electrode of the fourth transistor is electrically connected to the second node;

a first electrode of the fifth transistor is configured to receive the first constant potential signal, and a second electrode of the fifth transistor is electrically connected to the output terminal;

a gate electrode of the sixth transistor is configured to receive a first clock signal, a first electrode of the sixth transistor is configured to receive the first constant potential signal, and a second electrode of the sixth transistor is electrically connected to the output terminal;

a first electrode of the first capacitor is configured to receive the first control signal, and a second electrode of the first capacitor is electrically connected to the second node; and

a first electrode of the second capacitor is electrically connected to the first node, and a second electrode of the second capacitor is electrically connected to the output terminal.

3. The gate drive circuit according to claim 2 , further comprising a seventh transistor, wherein

a gate electrode of the seventh transistor is configured to receive a reset signal, a first electrode of the seventh transistor is configured to receive the first constant potential signal, and a second electrode of the seventh transistor is electrically connected to the first node.

4. The gate drive circuit according to claim 3 , further comprising an eighth transistor, wherein

a gate electrode of the eighth transistor is configured to receive the reset signal, a first electrode of the eighth transistor is configured to receive the first constant potential signal, and a second electrode of the eighth transistor is electrically connected to the output terminal.

5. The gate drive circuit according to claim 2 , wherein

a channel width-to-length ratio of the driving transistor is larger than that of any one of the other transistors.

6. The gate drive circuit according to claim 2 , wherein

during the display period, the first control signal is a square wave signal in inverse phase to the first clock signal.

7. The gate drive circuit according to claim 2 , wherein

the gate drive circuit is arranged in a non-display region around a display region of a touch display panel, wherein the display region comprises a plurality of touch electrodes and a plurality of touch signal leads electrically connected to the touch electrodes, the touch electrodes being configured to receive touch driving signals through the touch signal leads; and, wherein

during the touch-control period, a phase and a frequency of the touch scanning signal are the same as those of the touch driving signal respectively, and an amplitude of the touch scanning signal is less than or equal to that of the touch driving signal.

8. The gate drive circuit according to claim 2 , wherein

during the touch-control period, the touch scanning signal is the first constant potential signal.

9. A cascade gate drive circuit, comprising a plurality of gate drive circuits, wherein each gate drive circuit comprises a driving transistor and a switching transistor, wherein

a gate electrode of the switching transistor is configured to receive a first switching signal, a first electrode of the switching transistor is configured to receive a second switching signal, a second electrode of the switching transistor is electrically connected to a gate electrode of the driving transistor, a first electrode of the driving transistor is configured to receive a first control signal, and a second electrode of the driving transistor is electrically connected to an output terminal; and, wherein

during a display period, the first control signal is a display scanning signal, the first switching signal switches the switching transistor off, the driving transistor is switched on upon reception of a display switching signal, and the driving transistor outputs the display scanning signal; and

during a touch-control period, the first control signal is a touch scanning signal, the first switching signal switches the switching transistor on, the second switching signal switches the driving transistor on, and the driving transistor outputs the touch scanning signal.

10. The cascade gate drive circuit according to claim 9 , wherein each of the gate drive circuits further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor and a second capacitor; wherein

a gate electrode of the first transistor is configured to receive a first switch-on signal, a first electrode of the first transistor is configured to receive a first power supply signal, and a second electrode of the first transistor and the gate electrode of the driving transistor are both electrically connected to a first node;

a gate electrode of the second transistor is configured to receive a second switch-on signal, a first electrode of the second transistor is configured to receive a second power supply signal, and a second electrode of the second transistor and the gate electrode of the driving transistor are both electrically connected to the first node;

a gate electrode of the third transistor and a gate electrode of the fifth transistor are both connected to a second node, a first electrode of the third transistor is configured to receive a first constant potential signal, and a second electrode of the third transistor is electrically connected to the first node;

a gate electrode of the fourth transistor is electrically connected to the first node, a first electrode of the fourth transistor is configured to receive the first constant potential signal, and a second electrode of the fourth transistor is electrically connected to the second node;

a first electrode of the fifth transistor is configured to receive the first constant potential signal, and a second electrode of the fifth transistor is electrically connected to the output terminal;

a gate electrode of the sixth transistor is configured to receive a first clock signal, a first electrode of the sixth transistor is configured to receive the first constant potential signal, and a second electrode of the sixth transistor is electrically connected to the output terminal;

a first electrode of the first capacitor is configured to receive the first control signal, and a second electrode of the first capacitor is electrically connected to the second node; and

a first electrode of the second capacitor is electrically connected to the first node, and a second electrode of the second capacitor is electrically connected to the output terminal.

11. The cascade gate drive circuit according to claim 10 , further comprising a plurality of gate drive sub-circuits, wherein each of the gate drive sub-circuits comprises a sub-driving transistor, a sub-first transistor, a sub-second transistor, a sub-third transistor, a sub-fourth transistor, a sub-fifth transistor, a sub-sixth transistor, a sub-first capacitor and a sub-second capacitor; wherein

a gate electrode of the sub-driving transistor is electrically connected to a sub-first node, the first electrode of the sub-driving transistor is configured to receive a second clock signal, and the second electrode of the sub-driving transistor is electrically connected to the output terminal;

a gate electrode of the sub-first transistor is configured to receive a first switch-on signal, a first electrode of the sub-first transistor is configured to receive a first power supply signal, and a second electrode of the sub-first transistor is electrically connected to the sub-first node;

a gate electrode of the sub-second transistor is configured to receive a second switch-on signal, a first electrode of the sub-second transistor is configured to receive a second power supply signal, and a second electrode of the sub-second transistor is electrically connected to the sub-first node;

a gate electrode of the sub-third transistor and a gate electrode of the sub-fifth transistor are both connected to a sub-second node, a first electrode of the sub-third transistor is configured to receive a first constant potential signal, and a second electrode of the sub-third transistor is electrically connected to the sub-first node;

a gate electrode of the sub-fourth transistor is electrically connected to the sub-first node, a first electrode of the sub-fourth transistor is configured to receive the first constant potential signal, and a second electrode of the sub-fourth transistor is electrically connected to the sub-second node;

a first electrode of the sub-fifth transistor is configured to receive the first constant potential signal, and a second electrode of the sub-fifth transistor is electrically connected to the output terminal;

a gate electrode of the sub-sixth transistor is configured to receive a first clock signal, a first electrode of the sub-sixth transistor is configured to receive the first constant potential signal, and a second electrode of the sub-sixth transistor is electrically connected to the output terminal;

a first electrode of the sub-first capacitor is configured to receive the first control signal, and a second electrode of the sub-first capacitor is electrically connected to the sub-second node; and

a first electrode of the sub-second capacitor is electrically connected to the sub-first node, and a second electrode of the sub-second capacitor is electrically connected to the output terminal.

12. The cascade gate drive circuit according to claim 11 , wherein the gate electrode of the sub-driving transistor is configured to receive only the signals transmitted via the sub-first transistor, the sub-second transistor and the sub-third transistor.

13. The cascade gate drive circuit according to claim 11 , comprising a plurality of gate drive circuit groups, wherein each of the gate drive circuit groups comprises a plurality of the gate drive circuits scanned successively, and one gate drive sub-circuit is arranged between any two adjacent gate drive circuit groups.

14. A method for driving a cascade gate drive circuit, wherein the cascade gate drive circuit comprises a plurality of gate drive circuits, each gate drive circuit comprises a driving transistor and a switching transistor, wherein

a gate electrode of the switching transistor is configured to receive a first switching signal, a first electrode of the switching transistor is configured to receive a second switching signal, a second electrode of the switching transistor is electrically connected to a gate electrode of the driving transistor, a first electrode of the driving transistor is configured to receive a first control signal, and a second electrode of the driving transistor is electrically connected to an output terminal;

during a display period, the first control signal is a display scanning signal, the first switching signal switches the switching transistor off, the driving transistor is switched on upon reception of a display switching signal, and the driving transistor outputs the display scanning signal; and

during a touch-control period, the first control signal is a touch scanning signal, the first switching signal switches the switching transistor on, the second switching signal switches the driving transistor on, and the driving transistor outputs the touch scanning signal,

a duration of one frame comprises a display period and a touch-control period that are continuous to each other;

during the display period, the plurality of gate drive circuits are scanned successively to output the display scanning signals sequentially; and

during the touch-control period, the plurality of gate drive circuits are scanned simultaneously to output the touch scanning signal simultaneously.

15. A method for driving the cascade gate drive circuit according to claim 13 , wherein

a duration of one frame comprises a plurality of repeated groups of continuous display period, suspension period and touch-control period, wherein

during the display period, at least one gate drive circuit in the gate drive circuit groups is scanned successively, and the gate drive circuit outputs the display scanning signal sequentially;

after the last gate drive circuit in the gate drive circuit group is scanned, the suspension period is entered, during which the scanning is stopped at the gate drive sub-circuit next to the last gate drive circuit in the gate drive circuit group;

during the touch-control period, all of the gate drive circuits in all of the gate drive circuit groups are scanned simultaneously and output the touch scanning signals simultaneously; and

after the touch-control period ends, during the immediately next display period, the gate drive sub-circuit at which the scanning was stopped in the suspension period starts to output the display scanning signals.