IP Library › Granted Patent US 9,787,924
Granted Patent B2
US 9,787,924 · App. 14/959,290 · Granted Oct 10, 2017

Image sensor device, image processing device and method for manufacturing image sensor device

Inventor: Tsutomu Tezuka (Ibaraki, JP)
Assignee: Kabushiki Kaisha Toshiba
H04N5/37455H01L27/1464H01L27/1469H01L27/14612H01L27/14627H01L27/14634H01L27/14636H01L27/14641H01L27/14643H01L27/14685H01L27/14689H04N5/369
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,787,924
App. No.
14/959,290
Granted
Oct 10, 2017
Kind
B2
Abstract

According to one embodiment, an image sensor device includes a sensor array on a semiconductor substrate, the sensor array including blocks, each of the blocks including a pixel and outputting a signal of the pixel; a first insulating layer on the sensor array; semiconductor layers on the first insulating layer; analog-digital converting circuits on the semiconductor layers, the analog-digital converting circuits corresponding to the blocks and processing the signal; a second insulating layer on the first insulating layer and the analog-digital converting circuits; and interconnect portions electrically connecting the analog-digital converting circuits to the blocks via a region between the semiconductor layers, the interconnect portions extending across the first insulating layer and the second insulating layer.

Claims (81)

1. An image sensor device comprising:

a sensor array disposed on a semiconductor substrate, the sensor array including blocks, each of the blocks including at least one pixel and outputting a signal of the at least one pixel;

a first insulating layer disposed on the sensor array;

semiconductor layers disposed on the first insulating layer;

analog-digital converting circuits disposed on the semiconductor layers, the analog-digital converting circuits corresponding to the blocks and processing the signal;

a second insulating layer disposed on the first insulating layer and the analog-digital converting circuits; and

interconnect portions electrically connecting the analog-digital converting circuits to the blocks via a region between the semiconductor layers, the interconnect portions extending across the first insulating layer and the second insulating layer.

2. The device according to claim 1 , wherein

the each of the blocks includes M×N pixels (M and N are integers), and

the analog-digital converting circuits correspond to the blocks respectively.

3. The device according to claim 1 , wherein

the semiconductor substrate is a monocrystalline substrate, and

the semiconductor layers are monocrystalline layers or polycrystalline layers.

4. The device according to claim 1 , wherein

the semiconductor layers include at least Si and Sn, and

the semiconductor layers have a Si composition of 20% or more and a Sn composition of 2% or less.

5. The device according to claim 4 , wherein

the semiconductor layers further include Ge, and

the semiconductor layers are mixed crystal layers.

6. The device according to claim 1 , further comprising:

a lens array disposed on a side of a first face of the semiconductor substrate,

wherein

the analog-digital converting circuits are disposed on a side of a second face of the semiconductor substrate, and

the second face is opposed to the first face.

7. An image processing device comprising:

the image sensor device according to claim 1 ; and

a processor for image processing, the processor having a face on which bumps are disposed,

wherein the analog-digital converting circuits are electrically connected to the bumps.

8. An image sensor device comprising;

a sensor array disposed on a first semiconductor substrate, the sensor array including blocks, each of the blocks including at least one pixel and outputting a signal of the at least one pixel;

first bumps disposed on the first semiconductor substrate and connected to an output end of the each of the blocks;

an image processing circuit disposed on a second semiconductor substrate;

an first insulating layer disposed on the image processing circuit;

semiconductor layers disposed on the first insulating layer;

analog-digital converting circuits disposed on the semiconductor layers, the analog-digital converting circuits corresponding to the blocks and processing the signal;

a second insulating layer disposed on the first insulating layer and the analog-digital converting circuits;

interconnect portions electrically connecting the analog-digital converting circuit to the image processing circuit via a region between the semiconductor layers, the interconnect portions extending across the first insulating layer and the second insulating layer; and

second bumps connected to an input end of each of the analog-digital converting circuits, the second bumps being connected to the first bumps.

9. The device according to claim 8 , wherein

the each of the blocks includes M×N pixels (M and N are integers), and

the analog-digital converting circuits correspond to the blocks respectively.

10. The device according to claim 8 , wherein

the first and second semiconductor substrates are monocrystalline substrates, and

the semiconductor layers are monocrystalline layers or polycrystalline layers.

11. The device according to claim 8 , wherein

the semiconductor layers include at least Si and Sn, and

the semiconductor layers have a Si composition of 20% or more and a Sn composition of 2% or less.

12. The device according to claim 11 , wherein

the semiconductor layers further includes Ge, and

the semiconductor layers are mixed crystal layers.

13. The device according to claim 8 , further comprising:

a lens array disposed on a side of a first face of the semiconductor substrate,

wherein

the analog-digital converting circuits are disposed on a side of a second face of the semiconductor substrate, and

the second face is opposed to the first face.

14. A method for manufacturing an image sensor device comprising:

forming a sensor array on a semiconductor substrate, the sensor array including blocks, each of blocks including at least one pixel and outputting a signal of the at least one pixel;

forming a first insulating layer on the sensor array;

forming semiconductor layers on the first insulating layer;

forming analog-digital converting circuits on the semiconductor layers, the analog-digital converting circuits corresponding to the blocks and processing the signal;

forming a second insulating layer on the first insulating layer and the analog-digital converting circuits; and

forming interconnect portions across the first insulating layer and the second insulating layer to electrically connect the analog-digital converting circuits to the blocks via a region between the semiconductor layers.

15. The method according to claim 14 , wherein

the semiconductor substrate is a monocrystalline substrate, and

the semiconductor layers are monocrystalline layers or polycrystalline layers.

16. The method according to claim 14 , wherein

the semiconductor layers include at least Si and Sn, and

the semiconductor layers have a Si composition of 20% or more and a Sn composition of 2% or less.

17. The method according to claim 16 , wherein

the semiconductor layers further includes Ge, and

the semiconductor layers are mixed crystal layers.

18. The method according to claim 14 , wherein

a temperature range for forming of the semiconductor layers is from 250° C. to 400° C.

19. The method according to claim 14 , wherein

the forming of the semiconductor layers includes:

forming a layer selected from the group consisting of an amorphous Si layer, an amorphous Ge layer, an amorphous SiGe layer, an amorphous GeSn layer, an amorphous SiGeSn layer, or a stacked layer thereof.

dividing the layer into a plurality of layers, and

performing thermal treatment to crystallize the plurality of layers, the thermal treatment having a temperature range from 250° C. to 400° C.

20. The method according to claim 14 , further comprising:

forming a lens array on a side of a first face of the semiconductor substrate, the first face being opposed to a second face of the semiconductor substrate,

wherein the analog-digital converting circuits are formed on a side of the second face.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2015
From: TEZUKA, TSUTOMU
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 037330/0570 →
Priority Claims (1)
JP 2013-118789 · Jun 5, 2013 · national
Continuity (2)
Continuation PCTJP2014050921 · Jan 20, 2014
Related Publication 20160088253A1 · Mar 24, 2016