IP Library Granted Patent US 9,793,370
Granted Patent B2
US 9,793,370 · App. 14/721,796 · Granted Oct 17, 2017

Transistor with oxidized cap layer

Inventor: Wen-Chia Liao (Taoyuan, TW)
Assignee: DELTA ELECTRONICS, INC.
H01L29/66462H01L21/02241H01L21/02252H01L21/02255H01L21/28264H01L21/31105H01L29/2003H01L29/205H01L29/4236H01L29/513H01L29/518H01L29/7786H01L29/7787
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Quick Facts
Patent No.
US 9,793,370
App. No.
14/721,796
Granted
Oct 17, 2017
Kind
B2
Abstract

A semiconductor device includes a substrate, a channel layer, a spacer layer, a barrier layer, and an oxidized cap layer. The channel layer is disposed on or above the substrate. The spacer layer is disposed on the channel layer. The barrier layer is disposed on the spacer layer. The oxidized cap layer is disposed on the barrier layer. The oxidized cap layer is made of oxynitride.

Claims (14)

1. A semiconductor device, comprising:

a substrate;

a channel layer disposed on or above the substrate, wherein a two dimensional electron gas channel exists in the channel layer;

a spacer layer disposed on the channel layer and in contact with the channel layer;

a barrier layer disposed on the spacer layer and in contact with the spacer layer;

an oxidized cap layer disposed on the barrier layer and in contact with the barrier layer, wherein the oxidized cap layer is made of aluminum oxynitride;

a source and a drain disposed on or above the barrier layer;

a gate disposed at least on or above the oxidized cap layer and disposed between the source and the drain, wherein the spacer layer has an oxidation segment, the oxidized cap layer has a first recess, and the barrier layer has a second recess, the first recess and the second recess together expose at least a portion of the oxidation segment, and at least a portion of the gate is disposed in the first recess and the second recess; and

a passivation layer disposed on the oxidized cap layer, wherein at least a portion of the passivation layer is disposed between the oxidized cap layer and the gate, and at least a portion of the passivation layer is in contact with the barrier layer.

2. The semiconductor device of claim 1 , wherein a thickness of the spacer layer is less than 5 nm.

3. The semiconductor device of claim 1 , wherein the spacer layer is made of aluminum nitride.

4. The semiconductor device of claim 1 , wherein a thickness of the oxidized cap layer is less than 5 nm.

5. The semiconductor device of claim 1 , wherein the barrier layer is made of aluminum gallium nitride (Al x Ga (1-x) N), and 0.1≦x≦0.4.

6. The semiconductor device of claim 1 , wherein the passivation layer is conformally disposed in the first recess and the second recess, and at least a portion of the passivation layer is disposed between the gate electrode and the oxidation segment of the spacer layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2022
From: DELTA ELECTRONICS, INC.
To: ANCORA SEMICONDUCTORS INC.
Reel/Frame 061648/0861 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2015
From: LIAO, WEN-CHIA
To: DELTA ELECTRONICS, INC.
Reel/Frame 035771/0815 →
Continuity (2)
Provisional Application 62005294 · May 30, 2014
Related Publication 20150349107A1 · Dec 3, 2015