FinFET structure device
The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.
1. A FinFET device, comprising:
at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region;
a trench located in the fin structure and disposed between the first-type well region and the second-type well region;
an insulating layer disposed in the trench, wherein the insulating layer contacts the first-type well region and the second-type well region directly; and
a metal gate crossing over and disposed on the insulating layer, wherein the FinFET device is a high-voltage FinFET device having lateral diffusion laterally diffused metal oxide semiconductor (LDMOS) structure.
2. The FinFET device of claim 1 , wherein the metal gate has a vertical extension portion and a horizontal extension portion connected with the vertical extension portion.
3. The FinFET device of claim 2 , wherein the vertical extension portion extends into the fin structure.
4. The FinFET device of claim 1 , further comprising a plurality of dummy gates crossing over and disposed on the fin structure.
5. The FinFET device of claim 4 , wherein each dummy gate and the metal gate includes a metal gate material layer and a high-k material layer respectively, the high-k material layer disposed between the fin structure and the metal gate material layer.
6. The FinFET device of claim 4 , further comprising a source doped layer disposed in the first-type well region, and a drain doped layer disposed in the second-type well region, wherein the source doped layer is disposed between the metal gate and one of the dummy gate, and the drain doped layer is disposed between the metal gate and another dummy gate.
7. The FinFET device of claim 6 , wherein the first-type well region is an n-type well region, the second-type well region well region is a p-type well region, and the drain doped layer and the source doped layer are n-type doped layers.
8. The FinFET device of claim 7 , wherein the drain doped layer and the source doped layer are phosphorus-doped-silicon epitaxial layers.
9. The FinFET device of claim 6 , wherein the first-type well region is a p-type well region, the second-type well region well region is an n-type well region, and the drain doped layer and the source doped layer are p-type doped layers.
10. The FinFET device of claim 9 , wherein the drain doped layer and the source doped layer comprise silicon-germanium (SiGe) epitaxial layers.
11. A FinFET device, comprising:
at least one fin structure, wherein the fin structure has a first-type well region and a second-type well region adjacent to the first-type well region, and a well junction is disposed between the first-type well region and the second-type well region;
a trench located in the fin structure and disposed between the first-type well region and the second-type well region;
an insulating layer disposed in the trench, wherein the insulating layer contacts the first-type well region and the second-type well region directly; and
a metal gate crossing over and disposed on the insulating layer, wherein a sidewall of the metal gate is aligned with the well junction, wherein the FinFET device is a high-voltage FinFET device having lateral diffusion laterally diffused metal oxide semiconductor (LDMOS) structure.
12. The FinFET device of claim 11 , further comprising a plurality of dummy gates crossing over and disposed on the fin structure.
13. The FinFET device of claim 12 , further comprising a source doped layer disposed in the first-type well region, and a drain doped layer disposed in the second-type well region, wherein the source doped layer is disposed between the metal gate and one of the dummy gate, and the drain doped layer is disposed between the metal gate and another dummy gate.
14. The FinFET device of claim 13 , at least one dummy gate disposed between the metal gate and the drain doped layer.
15. The FinFET device of claim 14 , wherein parts of the at least one dummy gate are partially disposed in the trench.
16. The FinFET device of claim 13 , wherein the first-type well region is an n-type well region, the second-type well region well region is a p-type well region, and the drain doped layer and the source doped layer are n-type doped layers.
17. The FinFET device of claim 13 , wherein the first-type well region is a p-type well region, the second-type well region well region is an n-type well region, and the drain doped layer and the source doped layer are p-type doped layers.
18. The FinFET device of claim 12 , wherein each dummy gate and the metal gate includes a metal gate material layer and a high-k material layer respectively, the high-k material layer disposed between the fin structure and the metal gate material layer.
19. The FinFET device of claim 12 , wherein a top surface of the insulating layer is lower than a top surface of the fin structure.