Semiconductor device
A semiconductor device having stable electric characteristics is provided. The transistor includes first to third oxide semiconductor layers, a gate electrode, and a gate insulating layer. The second oxide semiconductor layer has a portion positioned between the first and third oxide semiconductor layers. The gate insulating layer has a region in contact with a top surface of the third oxide semiconductor layer. The gate electrode overlaps with a top surface of the portion with the gate insulating layer positioned therebetween. The gate electrode faces a side surface of the portion in a channel width direction with the gate insulating layer positioned therebetween. The second oxide semiconductor layer includes a region having a thickness greater than or equal to 2 nm and less than 8 nm. The length in the channel width direction of the second oxide semiconductor layer is less than 60 nm.
1. A transistor comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer over the second oxide semiconductor layer;
a gate insulating layer over and in contact with the third oxide semiconductor layer; and
a gate electrode over the gate insulating layer;
wherein a portion of the gate electrode faces a side surface of the second oxide semiconductor layer in a channel width direction with the gate insulating layer positioned therebetween,
wherein the portion of the gate electrode extends below a bottom surface of the second oxide semiconductor layer in a depth direction,
wherein the second oxide semiconductor layer includes a region having a thickness greater than or equal to 2 nm and less than 20 nm, and
wherein a length of the second oxide semiconductor layer in the channel width direction is less than 80 nm.
2. The transistor according to claim 1 , wherein a channel length of the transistor is greater than or equal to 10 nm and less than 100 nm.
3. The transistor according to claim 1 ,
wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises indium, zinc, and M, and
wherein M is one selected from the group consisting of Al, Ti, Ga, Y, Zr, La, Ce, Nd and Hf.
4. The transistor according to claim 3 , wherein the first oxide semiconductor layer and the third oxide semiconductor layer have a higher atomic ratio of M to In than the second oxide semiconductor layer.
5. The transistor according to claim 1 ,
wherein the first oxide semiconductor layer is thicker than the third oxide semiconductor layer.
6. The transistor according to claim 1 ,
wherein the first oxide semiconductor layer includes a region with a thickness of greater than or equal to 10 nm.
7. The transistor according to claim 1 ,
wherein the second oxide semiconductor layer is thicker than the third oxide semiconductor layer.
8. The transistor according to claim 1 , further comprising an insulating film below and in contact with the first oxide semiconductor layer,
wherein the insulating film comprises a projection below the first oxide semiconductor layer,
wherein a value obtained by subtracting a thickness of the gate insulating layer from the sum of a height of the projection and a thickness of the first oxide semiconductor layer has a positive value.
9. A transistor comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer over the second oxide semiconductor layer;
a gate insulating layer over and in contact with the third oxide semiconductor layer; and
a gate electrode over the gate insulating layer;
wherein a portion of the gate electrode faces a side surface of the second oxide semiconductor layer in a channel width direction with the gate insulating layer positioned therebetween,
wherein the portion of the gate electrode extends below a bottom surface of the second oxide semiconductor layer in a depth direction,
wherein the second oxide semiconductor layer includes a region having a thickness greater than or equal to 2 nm and less than 20 nm,
wherein a length of the second oxide semiconductor layer in the channel width direction is less than 80 nm, and
wherein a thickness of the third oxide semiconductor layer is less than 10 nm.
10. The transistor according to claim 9 ,
wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises indium, zinc, and M, and
wherein M is one selected from the group consisting of Al, Ti, Ga, Y, Zr, La, Ce, Nd and Hf.
11. The transistor according to claim 10 , wherein the first oxide semiconductor layer and the third oxide semiconductor layer have a higher atomic ratio of M to In than the second oxide semiconductor layer.
12. The transistor according to claim 9 ,
wherein the first oxide semiconductor layer is thicker than the third oxide semiconductor layer.
13. The transistor according to claim 9 ,
wherein the first oxide semiconductor layer includes a region with a thickness of greater than or equal to 10 nm.
14. The transistor according to claim 9 ,
wherein the second oxide semiconductor layer is thicker than the third oxide semiconductor layer.
15. The transistor according to claim 9 , further comprising an insulating film below and in contact with the first oxide semiconductor layer,
wherein the insulating film comprises a projection below the first oxide semiconductor layer,
wherein a value obtained by subtracting a thickness of the gate insulating layer from the sum of a height of the projection and a thickness of the first oxide semiconductor layer has a positive value.
16. A transistor comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer over the second oxide semiconductor layer;
a gate insulating layer over and in contact with the third oxide semiconductor layer; and
a gate electrode over the gate insulating layer;
wherein a portion of the gate electrode faces a side surface of the second oxide semiconductor layer in a channel width direction with the gate insulating layer positioned therebetween,
wherein the portion of the gate electrode extends below a bottom surface of the second oxide semiconductor layer in a depth direction,
wherein the second oxide semiconductor layer includes a region having a thickness greater than or equal to 2 nm and less than 20 nm,
wherein a length of the second oxide semiconductor layer in the channel width direction is less than 80 nm,
wherein a thickness of the third oxide semiconductor layer is less than 10 nm, and
wherein a channel length of the transistor is greater than or equal to 10 nm and less than 100 nm.
17. The transistor according to claim 16 ,
wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises indium, zinc, and M, and
wherein M is one selected from the group consisting of Al, Ti, Ga, Y, Zr, La, Ce, Nd and Hf.
18. The transistor according to claim 17 , wherein the first oxide semiconductor layer and the third oxide semiconductor layer have a higher atomic ratio of M to In than the second oxide semiconductor layer.
19. The transistor according to claim 16 ,
wherein the first oxide semiconductor layer is thicker than the third oxide semiconductor layer.
20. The transistor according to claim 16 ,
wherein the first oxide semiconductor layer includes a region with a thickness of greater than or equal to 10 nm.
21. The transistor according to claim 16 ,
wherein the second oxide semiconductor layer is thicker than the third oxide semiconductor layer.
22. The transistor according to claim 16 , further comprising an insulating film below and in contact with the first oxide semiconductor layer,
wherein the insulating film comprises a projection below the first oxide semiconductor layer,
wherein a value obtained by subtracting a thickness of the gate insulating layer from the sum of a height of the projection and a thickness of the first oxide semiconductor layer has a positive value.