Apparatus and method for compressing instruction for VLIW processor, and apparatus and method for fetching instruction

1. An instruction compression apparatus comprising:

an indicator generator configured to generate an indicator code that indicates an issue width of an instruction bundle to be executed in a very long instruction word (VLIW) processor, and a number of No-Operation (NOP) instruction bundles following the instruction bundle;

an instruction compressor configured to compress the instruction bundle by removing at least one of NOP instructions from the instruction bundle and the NOP instruction bundles following the instruction bundle; and

an instruction converter configured to include the generated indicator code in the compressed instruction bundle,

wherein the instruction converter is configured to replace a stop bit of each instruction of the compressed instruction bundle with a corresponding bit value of the indicator code.

2. The instruction compression apparatus of claim 1 , wherein the issue width of the instruction bundle is determined based on at least one of a maximum issue width available in the VLIW processor, and a number of NOP instructions included in the instruction bundle.

3. The instruction compression apparatus of claim 2 , wherein a value of the issue width of the instruction bundle is variably determined as a multiple of two or more, within the maximum issue width available in the VLIW processor.

4. The instruction compression apparatus of claim 1 , wherein a maximum number of NOP instruction bundles removable by the instruction compressor is determined based on the issue width of the instruction bundle.

5. The instruction compression apparatus of claim 1 , wherein the instructions of the compressed instruction bundle are remaining instructions that are not removed by the instruction compressor.

6. An instruction fetching apparatus for a processor, the instruction fetching apparatus comprising:

an instruction selector configured to select, from an instruction cache, an instruction bundle at an address indicated by a program counter (PC);

an instruction buffer configured to store the instruction bundle selected by the instruction selector; and

a No-Operation (NOP) bundle controller configured to control, based on an indicator code corresponding to the instruction bundle forwarded from the instruction buffer to an instruction decoder in a current cycle, fetch of another instruction bundle in a subsequent cycle,

wherein the NOP bundle controller is configured to extract the indicator code based on a value of a stop bit of each instruction included in the instruction bundle forwarded to the instruction decoder in the current cycle, and

wherein the NOP bundle controller is configured to determine, based on a value of a stop bit of a first instruction included in the instruction bundle in the current cycle, a size of the indicator code to be extracted.

7. The instruction fetching apparatus of claim 6 , wherein in a case where the instruction bundle is not at the address indicated by the PC, the instruction selector is configured to fetch the instruction bundle from an external memory, write the fetched instruction bundle in the instruction cache, and select the fetched instruction bundle.

8. The instruction fetching apparatus of claim 6 , wherein the NOP bundle controller is configured to determine, based on the extracted indicator code, an NOP bundle cycle in which an NOP instruction bundle is present after the current cycle, and to prevent the NOP instruction bundle from being fetched from the instruction buffer during the determined NOP bundle cycle.

9. The instruction fetching apparatus of claim 8 , wherein the NOP bundle controller is configured to control the instruction decoder to retain an instruction bundle forwarded in a previous cycle while preventing the NOP instruction bundle from being fetched during the determined NOP bundle cycle, and to transmit a signal to the instruction decoder so as to notify that the retained instruction bundle is not valid during the NOP bundle cycle.

10. An instruction compression method comprising:

determining at least one of No-Operation (NOP) instructions included in an instruction bundle to be executed in a very long instruction word (VLIW) processor and a number of NOP instruction bundles following the instruction bundle;

generating an indicator code that indicates an issue width of the instruction bundle and the number of the NOP instruction bundles following the instruction bundle; and

compressing the instruction bundle by removing the at least one of the NOP instructions from the instruction bundle and the NOP instruction bundles following the instruction bundle,

wherein the compressing replaces a stop bit of each instruction of the compressed instruction bundle with a corresponding bit value of the indicator code.

11. The instruction compression method of claim 10 , wherein the issue width of the instruction bundle is determined based on at least one of a maximum issue width available in the VLIW processor and a number of the NOP instructions included in the instruction bundle.

12. The instruction compression method of claim 10 , wherein a maximum number of NOP instruction bundles removable in the compressing is determined based on a determined issue width of the instruction bundle.